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* Clarify the LSDASection NULL checkAnton Korobeynikov2011-01-301-0/+2
| | | | llvm-svn: 124569
* Respect the -tail-dup-size command line option even when optimizing for size.Jakob Stoklund Olesen2011-01-301-1/+2
| | | | | | | This is similar to the -unroll-threshold option. There should be no change in behavior when -tail-dup-size is not explicit on the llc command line. llvm-svn: 124564
* Teach DAGCombine to fold fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, ↵Benjamin Kramer2011-01-301-0/+23
| | | | | | | | | | | | | | | | | | c1+c2) when c1 equals the amount of bits that are truncated off. This happens all the time when a smul is promoted to a larger type. On x86-64 we now compile "int test(int x) { return x/10; }" into movslq %edi, %rax imulq $1717986919, %rax, %rax movq %rax, %rcx shrq $63, %rcx sarq $34, %rax <- used to be "shrq $32, %rax; sarl $2, %eax" addl %ecx, %eax This fires 96 times in gcc.c on x86-64. llvm-svn: 124559
* Add the missing sub identity "A-(A-B) -> B" to DAGCombine.Benjamin Kramer2011-01-291-0/+3
| | | | | | | | This happens e.g. for code like "X - X%10" where we lower the modulo operation to a series of multiplies and shifts that are then subtracted from X, leading to this missed optimization. llvm-svn: 124532
* Re-apply r124518 with fix. Watch out for invalidated iterator.Evan Cheng2011-01-291-4/+7
| | | | llvm-svn: 124526
* Revert r124518. It broke Linux self-host.Evan Cheng2011-01-291-7/+4
| | | | llvm-svn: 124522
* Re-commit r124462 with fixes. Tail recursion elim will now dup ret into ↵Evan Cheng2011-01-291-4/+7
| | | | | | unconditional predecessor to enable TCE on demand. llvm-svn: 124518
* Revert r124462. There are a few big regressions that I need to fix first.Evan Cheng2011-01-281-7/+4
| | | | llvm-svn: 124478
* Fix build with stdcxx by using llvm::next. Patch by Joerg Sonnenberger!Nick Lewycky2011-01-281-1/+2
| | | | llvm-svn: 124472
* Print the visibility of declarations.Rafael Espindola2011-01-281-1/+14
| | | | llvm-svn: 124468
* - Stop simplifycfg from duplicating "ret" instructions into unconditionalEvan Cheng2011-01-281-4/+7
| | | | | | | | branches. PR8575, rdar://5134905, rdar://8911460. - Allow codegen tail duplication to dup small return blocks after register allocation is done. llvm-svn: 124462
* Remove a temporary workaround for a lencod miscompile. Depends on the fix in ↵Andrew Trick2011-01-271-2/+0
| | | | | | r124442. llvm-svn: 124443
* VirtRegRewriter fix: update kill flags, which are used by the scavenger.Andrew Trick2011-01-271-64/+88
| | | | | | | | | | | | | | | | | | | | | | | rdar://problem/8893967: JM/lencod miscompile at -arch armv7 -mthumb -O3 Added ResurrectKill to remove kill flags after we decide to reused a physical register. And (hopefully) ensure that we call it in all the right places. Sorry, I'm not checking in a unit test given that it's a miscompile I can't reproduce easily with a toy example. Failures in the rewriter depend on a series of heuristic decisions maked during one of the many upstream phases in codegen. This case would require coercing regalloc to generate a couple of rematerialzations in a way that causes the scavenger to reuse the same register at just the wrong point. The general way to test this is to implement kill flags verification. Then we could have a simple, robust compile-only unit test. That would be worth doing if the whole pass was not about to disappear. At this point we focus verification work on the next generation of regalloc. llvm-svn: 124442
* Speculatively revert r124380.Devang Patel2011-01-272-4/+1
| | | | llvm-svn: 124397
* While legalizing SDValues do not drop SDDbgValues, trasfer them to new legal ↵Devang Patel2011-01-272-1/+4
| | | | | | | | nodes. Take 2. This includes fix for dragonegg crash. llvm-svn: 124380
* Avoid modifying the OneClassForEachPhysReg map while iterating over it.Bob Wilson2011-01-271-2/+6
| | | | | | | | | Linear scan regalloc is currently assuming that any register aliased with a member of a regclass must also be in at least one regclass. That is not always true. For example, for X86, RIP is in a regclass but IP is not. If you're unlucky, this can cause a crash by invalidating the iterator. llvm-svn: 124365
* Try harder to not have unused variables.Matt Beaumont-Gay2011-01-271-0/+2
| | | | llvm-svn: 124350
* Opt-mode -Wunused-variable cleanupMatt Beaumont-Gay2011-01-271-4/+2
| | | | llvm-svn: 124346
* Reapply 124301Devang Patel2011-01-271-1/+5
| | | | llvm-svn: 124339
* Initialize variable to get rid of clang warning.Bill Wendling2011-01-261-1/+1
| | | | llvm-svn: 124331
* Revert 124301.Devang Patel2011-01-261-5/+1
| | | | llvm-svn: 124327
* Revert r124302Devang Patel2011-01-261-3/+0
| | | | llvm-svn: 124320
* [AVX] Add INSERT_SUBVECTOR and support it on x86. This provides aDavid Greene2011-01-262-0/+73
| | | | | | | | default implementation for x86, going through the stack in a similr fashion to how the codegen implements BUILD_VECTOR. Eventually this will get matched to VINSERTF128 if AVX is available. llvm-svn: 124307
* While legalizing SDValues do not drop SDDbgValues, trasfer them to new legal ↵Devang Patel2011-01-261-0/+3
| | | | | | nodes. llvm-svn: 124302
* Process valid SDDbgValues even if the node does not have any order assigned.Devang Patel2011-01-261-1/+5
| | | | llvm-svn: 124301
* Refactor.Devang Patel2011-01-261-19/+30
| | | | llvm-svn: 124300
* [AVX] Support EXTRACT_SUBVECTOR on x86. This provides a defaultDavid Greene2011-01-262-5/+24
| | | | | | | | implementation of EXTRACT_SUBVECTOR for x86, going through the stack in a similr fashion to how the codegen implements BUILD_VECTOR. Eventually this will get matched to VEXTRACTF128 if AVX is available. llvm-svn: 124292
* Rename member variables to follow the rest of LLVM.Jakob Stoklund Olesen2011-01-262-295/+295
| | | | | | No functional change. llvm-svn: 124257
* Provide an interface to transfer SDDbgValue from one SDNode to another.Devang Patel2011-01-252-0/+25
| | | | llvm-svn: 124245
* Resolve DanglingDbgValue of PHI nodes where the use follows dbg.value ↵Devang Patel2011-01-251-1/+3
| | | | | | intrinisic. llvm-svn: 124203
* This assertion is too restrictive, it does not apply for dangling dbg value ↵Devang Patel2011-01-251-8/+0
| | | | | | nodes (nodes where dbg.value intrinsic preceds use of the value). llvm-svn: 124202
* Support printing exception section into the current one. This is the case ↵Anton Korobeynikov2011-01-241-1/+2
| | | | | | when LSDASection is blank llvm-svn: 124150
* Speculatively revert r124138.Devang Patel2011-01-241-3/+1
| | | | llvm-svn: 124142
* Resolve DanglingDbgValue of PHI nodes where the use follows dbg.value ↵Devang Patel2011-01-241-1/+3
| | | | | | intrinisic. llvm-svn: 124138
* Temporarily workaround JM/lencod miscompile (SIGSEGV).Andrew Trick2011-01-241-0/+2
| | | | | | rdar://problem/8893967 llvm-svn: 124137
* Add support for the --noexecstack option.Rafael Espindola2011-01-231-1/+2
| | | | llvm-svn: 124077
* Null initialize a few variables flagged byTed Kremenek2011-01-231-1/+1
| | | | | | | | | | clang's -Wuninitialized-experimental warning. While these don't look like real bugs, clang's -Wuninitialized-experimental analysis is stricter than GCC's, and these fixes have the benefit of being general nice cleanups. llvm-svn: 124073
* Delay the creation of eh_frame so that the user can change the defaults.Rafael Espindola2011-01-231-20/+23
| | | | | | Add support for SHT_X86_64_UNWIND. llvm-svn: 124059
* Remove more duplicated code.Rafael Espindola2011-01-231-29/+29
| | | | llvm-svn: 124056
* Remove duplicated code.Rafael Espindola2011-01-231-34/+35
| | | | llvm-svn: 124054
* Enable support for precise scheduling of the instruction selectionAndrew Trick2011-01-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | DAG. Disable using "-disable-sched-cycles". For ARM, this enables a framework for modeling the cpu pipeline and counting stalls. It also activates several heuristics to drive scheduling based on the model. Scheduling is inherently imprecise at this stage, and until spilling is improved it may defeat attempts to schedule. However, this framework provides greater control over tuning codegen. Although the flag is not target-specific, it should have very little affect on the default scheduler used by x86. The only two changes that affect x86 are: - scheduling a high-latency operation bumps the current cycle so independent operations can have their latency covered. i.e. two independent 4 cycle operations can produce results in 4 cycles, not 8 cycles. - Two operations with equal register pressure impact and no latency-based stalls on their uses will be prioritized by depth before height (height is irrelevant if no stalls occur in the schedule below this point). llvm-svn: 123971
* Convert -enable-sched-cycles and -enable-sched-hazard to -disableAndrew Trick2011-01-213-34/+51
| | | | | | | | | | | flags. They are still not enable in this revision. Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with the scheduler's model of operand latency in the selection DAG. Generalized unit tests to work with sched-cycles. llvm-svn: 123969
* SplitKit requires that all defs are in place before calling useIntv().Jakob Stoklund Olesen2011-01-201-10/+22
| | | | | | | | | | | The value mapping gets confused about which original values have multiple new definitions so they may need phi insertions. This could probably be simplified by letting enterIntvBefore() take a live range to be added following the instruction. As long as the range stays inside the same basic block, value mapping shouldn't be a problem. llvm-svn: 123926
* Add LiveIntervalMap::dumpCache() to print out the cache used by the ssa ↵Jakob Stoklund Olesen2011-01-202-0/+24
| | | | | | update algorithm. llvm-svn: 123925
* My editor's indent went crazy. Fix.Eric Christopher2011-01-201-1/+1
| | | | llvm-svn: 123909
* Expand invalid return values for umulo and smulo. Handle these similarlyEric Christopher2011-01-202-0/+28
| | | | | | | | | | to add/sub by doing the normal operation and then checking for overflow afterwards. This generally relies on the DAG handling the later invalid operations as well. Fixes the 64-bit part of rdar://8622122 and rdar://8774702. llvm-svn: 123908
* Sorry, several patches in one.Evan Cheng2011-01-202-42/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | TargetInstrInfo: Change produceSameValue() to take MachineRegisterInfo as an optional argument. When in SSA form, targets can use it to make more aggressive equality analysis. Machine LICM: 1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead. 2. Fix a bug which prevent CSE of instructions which are not re-materializable. 3. Use improved form of produceSameValue. ARM: 1. Teach ARM produceSameValue to look pass some PIC labels. 2. Look for operands from different loads of different constant pool entries which have same values. 3. Re-implement PIC GA materialization using movw + movt. Combine the pair with a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible to re-materialize the instruction, allow machine LICM to hoist the set of instructions out of the loop and make it possible to CSE them. It's a bit hacky, but it significantly improve code quality. 4. Some minor bug fixes as well. With the fixes, using movw + movt to materialize GAs significantly outperform the load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap and 176.gcc ~10%. llvm-svn: 123905
* Selection DAG scheduler register pressure heuristic fixes.Andrew Trick2011-01-201-8/+27
| | | | | | | | Added a check for already live regs before claiming HighRegPressure. Fixed a few cases of checking the wrong number of successors. Added some tracing until these heuristics are better understood. llvm-svn: 123892
* Check that a live range exists before shortening it. This fixes PR8989.Jakob Stoklund Olesen2011-01-201-3/+5
| | | | | | The live range may have been deleted earlier because of rematerialization. llvm-svn: 123891
* Add hidden -verify-coalescing to run the machine code verifier before and afterJakob Stoklund Olesen2011-01-201-0/+10
| | | | | | register coalescing. llvm-svn: 123890
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