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* Use MDNode * directly as an RecordSourceLine() argument.Devang Patel2009-09-305-12/+11
| | | | llvm-svn: 83182
* Remove dead code.Devang Patel2009-09-301-17/+0
| | | | llvm-svn: 83181
* Add a new virtual EmitStartOfAsmFile method to the AsmPrinter and use thisBob Wilson2009-09-301-2/+4
| | | | | | | | | | | | | | | | to emit target-specific things at the beginning of the asm output. This fixes a problem for PPC, where the text sections are not being kept together as expected. The base class doInitialization code calls DW->BeginModule() which emits a bunch of DWARF section directives. The PPC doInitialization code then emits all the TEXT section directives, with the intention that they will be kept together. But as I understand it, the Darwin assembler treats the default TEXT section as a special case and moves it to the beginning of the file, which means that all those DWARF sections are in the middle of the text. With this change, the EmitStartOfAsmFile hook is called before the DWARF section directives are emitted, so that all the PPC text section directives come out right at the beginning of the file. llvm-svn: 83176
* Fix a comment.Bob Wilson2009-09-301-1/+1
| | | | llvm-svn: 83171
* Silence comparison always false warning in -Asserts mode.Reid Kleckner2009-09-301-4/+4
| | | | llvm-svn: 83164
* Add additional assert() to verify no extraneous use of a scavenged register.Jim Grosbach2009-09-301-2/+9
| | | | llvm-svn: 83163
* Fix integer overflow in instruction scheduling. This can happen if we haveReid Kleckner2009-09-305-20/+33
| | | | | | | | | | basic blocks that are so long that their size overflows a short. Also assert that overflow does not happen in the future, as requested by Evan. This fixes PR4401. llvm-svn: 83159
* Add a target hook to add pre- post-regalloc scheduling passes.Evan Cheng2009-09-301-0/+4
| | | | llvm-svn: 83144
* replace TRI->isVirtualRegister() with TargetRegisterInfo::isVirtualRegister()Jim Grosbach2009-09-302-5/+4
| | | | | | per customary usage llvm-svn: 83137
* fix compiler warningJim Grosbach2009-09-301-1/+1
| | | | llvm-svn: 83132
* Simplify.Devang Patel2009-09-301-6/+0
| | | | llvm-svn: 83123
* Remove -post-RA-schedule flag and add a TargetSubtarget method to enable ↵David Goodwin2009-09-302-9/+7
| | | | | | post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8. llvm-svn: 83122
* Add a way for a frontend to generate more complex dwarf locationMike Stump2009-09-302-6/+70
| | | | | | | | | | | | | | | | | | information. This allows arbitrary code involving DW_OP_plus_uconst and DW_OP_deref. The scheme allows for easy extention to include, any, or all of the DW_OP_ opcodes. I thought about just exposing all of them, but, wasn't sure if people wanted the dwarf opcodes exposed in the api. Is that a layering violation? With this scheme, the entire existing block scheme used by llvm-gcc can be switched over to the new scheme. I think that would be cleaner, as then the compiler specific bits are not present in llvm proper. Before the old code can be yanked however, similar code in clang would have to be removed. Next up, more testing. llvm-svn: 83120
* Additional check for regno==0Jim Grosbach2009-09-291-1/+1
| | | | llvm-svn: 83103
* Remove unnecessary cast.Devang Patel2009-09-291-4/+2
| | | | llvm-svn: 83100
* Remove std::string uses from DebugInfo interface.Devang Patel2009-09-294-69/+42
| | | | llvm-svn: 83083
* Simplify the tracking of virtual frame index registers. Ranges cannot overlap,Jim Grosbach2009-09-291-20/+31
| | | | | | | so a simple "current register" will suffice. Also add some additional sanity-checking assertions to make sure things are as we expect. llvm-svn: 83081
* Moving register scavenging to a post pass results in virtual registers inJim Grosbach2009-09-291-2/+3
| | | | | | | the instruction we're scavenging for. The scavenger needs to know to avoid them when analyzing register usage. llvm-svn: 83077
* s/class Metadata/class MetadataContext/gDevang Patel2009-09-281-2/+2
| | | | llvm-svn: 83019
* Do not use global typedef for MDKindID.Devang Patel2009-09-281-2/+2
| | | | llvm-svn: 83016
* Use KILL instead of IMPLICIT_DEF in LowerSubregs pass.Jakob Stoklund Olesen2009-09-282-14/+13
| | | | llvm-svn: 83007
* Use VerifySchedule instead of doing the work manually.Dan Gohman2009-09-281-33/+3
| | | | llvm-svn: 82995
* Coalescer should not delete extract_subreg, insert_subreg, and subreg_to_reg ofEvan Cheng2009-09-281-3/+16
| | | | | | | | | | | physical registers. This is especially critical for the later two since they start the live interval of a super-register. e.g. %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1 If this instruction is eliminated, the register scavenger will not be happy as D0 is not defined previously. This fixes PR5055. llvm-svn: 82968
* Use explicit structs instead of std::pair to map callee saved regs to spill ↵Tilmann Scheller2009-09-271-4/+4
| | | | | | slots. llvm-svn: 82909
* Convert comparisons like (x == infinity) to (x >= infinity) on targetsDan Gohman2009-09-261-0/+37
| | | | | | where FCMP_OEQ is not legal and FCMP_OGE is, such as x86. llvm-svn: 82861
* Don't hoist or sink instructions with physreg uses if the physreg isDan Gohman2009-09-262-6/+24
| | | | | | | allocatable. Even if it doesn't appear to have any defs, it may latter on after register allocation. llvm-svn: 82834
* Unbreak MachineLICM for instructions that reference RIP on x86-64 too.Dan Gohman2009-09-251-2/+21
| | | | llvm-svn: 82825
* Move MachineMemOperand::getAlignment out of line, to avoid needingDan Gohman2009-09-251-0/+6
| | | | | | MathExtras.h in MachineMemOperand.h. llvm-svn: 82822
* Remove unused variable.Daniel Dunbar2009-09-251-2/+0
| | | | llvm-svn: 82821
* Fix MachineSink to be able to sink instructions that use physical registersDan Gohman2009-09-251-1/+14
| | | | | | | | which have no defs anywhere in the function. In particular, this fixes sinking of instructions that reference RIP on x86-64, which is currently being modeled as a register. llvm-svn: 82815
* Simplify a few more uses of reg_iterator.Dan Gohman2009-09-253-12/+8
| | | | llvm-svn: 82812
* Simplify this code by using use_iterator instead of reg_iteratorDan Gohman2009-09-251-4/+2
| | | | | | and skipping the defs. llvm-svn: 82811
* Flip -disable-post-RA-scheduler to -post-RA-scheduler.Evan Cheng2009-09-251-5/+7
| | | | llvm-svn: 82803
* Improve MachineMemOperand handling.Dan Gohman2009-09-2511-316/+435
| | | | | | | | | | | | | | | | | | | | | - Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions. This eliminates MachineInstr's std::list member and allows the data to be created by isel and live for the remainder of codegen, avoiding a lot of copying and unnecessary translation. This also shrinks MemSDNode. - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated fields for MachineMemOperands. - Change MemSDNode to have a MachineMemOperand member instead of its own fields with the same information. This introduces some redundancy, but it's more consistent with what MachineInstr will eventually want. - Ignore alignment when searching for redundant loads for CSE, but remember the greatest alignment. Target-specific code which previously used MemOperandSDNodes with generic SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range so that the SelectionDAG framework knows that MachineMemOperand information is available. llvm-svn: 82794
* Rename getTargetNode to getMachineNode, for consistency with theDan Gohman2009-09-251-44/+44
| | | | | | | | naming scheme used in SelectionDAG, where there are multiple kinds of "target" nodes, but "machine" nodes are nodes which represent a MachineInstr. llvm-svn: 82790
* Make sure sin, cos, sqrt calls are marked readonlyDale Johannesen2009-09-251-3/+6
| | | | | | | before producing FSIN, FCOS, FSQRT. If they aren't so marked we have to assume they might set errno. llvm-svn: 82781
* Generate FSQRT from calls to the sqrt function, whichDale Johannesen2009-09-251-0/+9
| | | | | | | | | | | | allows appropriate backends to generate a sqrt instruction. On x86, this isn't done at -O0 because we go through FastISel instead. This is a behavior change from before this series of sqrt patches started. I think this is OK considering that compile speed is most important at -O0, but could be convinced otherwise. llvm-svn: 82778
* pr4926: ARM requires the stack pointer to be aligned, even for leaf functions.Bob Wilson2009-09-251-14/+20
| | | | | | | | | | | | | | | | | | | | For the AAPCS ABI, SP must always be 4-byte aligned, and at any "public interface" it must be 8-byte aligned. For the older ARM APCS ABI, the stack alignment is just always 4 bytes. For X86, we currently align SP at entry to a function (e.g., to 16 bytes for Darwin), but no stack alignment is needed at other times, such as for a leaf function. After discussing this with Dan, I decided to go with the approach of adding a new "TransientStackAlignment" field to TargetFrameInfo. This value specifies the stack alignment that must be maintained even in between calls. It defaults to 1 except for ARM, where it is 4. (Some other targets may also want to set this if they have similar stack requirements. It's not currently required for PPC because it sets targetHandlesStackFrameRounding and handles the alignment in target-specific code.) The existing StackAlignment value specifies the alignment upon entry to a function, which is how we've been using it anyway. llvm-svn: 82767
* Fix combiner-aa issue with bases which are different, but can alias.Nate Begeman2009-09-251-14/+34
| | | | | | | Previously, it treated GV+28 GV+0 as different bases, and assumed they could not alias. llvm-svn: 82753
* Add a version of dumpr() that has a SelectionDAG* argument.Dan Gohman2009-09-251-0/+5
| | | | llvm-svn: 82742
* Start of revamping the register scavenging in PEI. ARM Thumb1 is the drivingJim Grosbach2009-09-242-3/+63
| | | | | | | | | | | | | | | | | | | interest for this, as it currently reserves a register rather than using the scavenger for matierializing constants as needed. Instead of scavenging registers on the fly while eliminating frame indices, new virtual registers are created, and then a scavenged collectively in a post-pass over the function. This isolates the bits that need to interact with the scavenger, and sets the stage for more intelligent use, and reuse, of scavenged registers. For the time being, this is disabled by default. Once the bugs are worked out, the current scavenging calls in replaceFrameIndices() will be removed and the post-pass scavenging will be the default. Until then, -enable-frame-index-scavenging enables the new code. Currently, only the Thumb1 back end is set up to use it. llvm-svn: 82734
* Delete space after function name, before (, reflow a comment andMike Stump2009-09-241-14/+6
| | | | | | delete a few blank lines. llvm-svn: 82729
* Fix spacing.Mike Stump2009-09-241-1/+1
| | | | llvm-svn: 82727
* Make the end-of-itinerary mark explicit. Some cleanup.David Goodwin2009-09-241-5/+3
| | | | llvm-svn: 82709
* Fix a hypothetical problem for targets with StackGrowsUp and a non-zeroBob Wilson2009-09-241-4/+5
| | | | | | | | | | | | | LocalAreaOffset. (We don't have any of those right now.) PEI::calculateFrameObjectOffsets includes the absolute value of the LocalAreaOffset in the cumulative offset value used to calculate the stack frame size. It then adds the raw value of the LocalAreaOffset to the stack size. For a StackGrowsDown target, that raw value is negative and has the effect of cancelling out the absolute value that was added earlier, but that obviously won't work for a StackGrowsUp target. Change to subtract the absolute value of the LocalAreaOffset. llvm-svn: 82693
* unconditionally compute MMI even if the target doesn't support EH or Debug ↵Chris Lattner2009-09-241-9/+6
| | | | | | info, because the target may use it for other things, this fixes PR5036 llvm-svn: 82684
* Fix PR5024 with a big hammer: disable the double-def assertion in the scavenger.Evan Cheng2009-09-241-39/+4
| | | | | | | | | | | | | | | | | | | | | | LiveVariables add implicit kills to correctly track partial register kills. This works well enough and is fairly accurate. But coalescer can make it impossible to maintain these markers. e.g. BL <ga:sss1>, %R0<kill,undef>, %S0<kill>, %R0<imp-def>, %R1<imp-def,dead>, %R2<imp-def,dead>, %R3<imp-def,dead>, %R12<imp-def,dead>, %LR<imp-def,dead>, %D0<imp-def>, ... ... %reg1031<def> = FLDS <cp#1>, 0, 14, %reg0, Mem:LD4[ConstantPool] ... %S0<def> = FCPYS %reg1031<kill>, 14, %reg0, %D0<imp-use,kill> When reg1031 and S0 are coalesced, the copy (FCPYS) will be eliminated the the implicit-kill of D0 is lost. In this case it's possible to move the marker to the FLDS. But in many cases, this is not possible. Suppose %reg1031<def> = FOO <cp#1>, %D0<imp-def> ... %S0<def> = FCPYS %reg1031<kill>, 14, %reg0, %D0<imp-use,kill> When FCPYS goes away, the definition of S0 is the "FOO" instruction. However, transferring the D0 implicit-kill to FOO doesn't work since it is the def of D0 itself. We need to fix this in another time by introducing a "kill" pseudo instruction to track liveness. Disabling the assertion is not ideal, but machine verifier is doing that job now. It's important to know double-def is not a miscomputation since it means a register should be free but it's not tracked as free. It's a performance issue instead. llvm-svn: 82677
* Clean up LiveVariables and change how it deals with partial updates and ↵Evan Cheng2009-09-242-200/+77
| | | | | | kills. This also eliminate the horrible check which scan forward to the end of the basic block. It should be faster and more accurate. llvm-svn: 82676
* Use getStoreSize() instead of getStoreSizeInBits()/8.Dan Gohman2009-09-233-5/+5
| | | | llvm-svn: 82656
* Rename several variables from EVT to more descriptive names, now that EVTDan Gohman2009-09-234-38/+39
| | | | | | | is also the name of their type, as declarations like "EVT EVT" look really odd. llvm-svn: 82654
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