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* The final step to close D41278 [MachineCombiner] Improve debug output (NFC).Andrew V. Tischenko2018-02-262-4/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D41278 llvm-svn: 326074
* [DebugInfo] Stable sort symbols to remove non-deterministic orderingMandeep Singh Grang2018-02-251-1/+1
| | | | | | | | | | | | | | | | Summary: This fixes failure in DebugInfo/X86/multiple-aranges.ll uncovered by D39245. Reviewers: rafael, echristo, probinson Reviewed By: probinson Subscribers: probinson, llvm-commits, JDevlieghere Tags: #debug-info Differential Revision: https://reviews.llvm.org/D39950 llvm-svn: 326056
* [TargetLowering] SimplifyDemandedVectorElts - pass demanded elts through ↵Simon Pilgrim2018-02-241-0/+13
| | | | | | ADD/SUB ops llvm-svn: 326044
* [TargetLowering] SimplifyDemandedVectorElts - pass demanded elts through ↵Simon Pilgrim2018-02-241-0/+5
| | | | | | TRUNCATE ops llvm-svn: 326043
* [WebAssembly] Add exception handling option and featureHeejin Ahn2018-02-242-0/+6
| | | | | | | | | | | | | | Summary: Add a llc command line option and WebAssembly architecture feature for exception handling. Reviewers: dschuff Subscribers: jfb, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D43683 llvm-svn: 326004
* [DebugInfo] Support DWARF v5 source code embedding extensionScott Linder2018-02-233-6/+9
| | | | | | | | | | | | | | | | | | | In DWARF v5 the Line Number Program Header is extensible, allowing values with new content types. In this extension a content type is added, DW_LNCT_LLVM_source, which contains the embedded source code of the file. Add new optional attribute for !DIFile IR metadata called source which contains source text. Use this to output the source to the DWARF line table of code objects. Analogously extend METADATA_FILE in Bitcode and .file directive in ASM to support optional source. Teach llvm-dwarfdump and llvm-objdump about the new values. Update the output format of llvm-dwarfdump to make room for the new attribute on file_names entries, and support embedded sources for the -source option in llvm-objdump. Differential Revision: https://reviews.llvm.org/D42765 llvm-svn: 325970
* [MachineOperand][Target] MachineOperand::isRenamable semantics changesGeoff Berry2018-02-235-30/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add a target option AllowRegisterRenaming that is used to opt in to post-register-allocation renaming of registers. This is set to 0 by default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq fields of all opcodes to be set to 1, causing MachineOperand::isRenamable to always return false. Set the AllowRegisterRenaming flag to 1 for all in-tree targets that have lit tests that were effected by enabling COPY forwarding in MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC, RISCV, Sparc, SystemZ and X86). Add some more comments describing the semantics of the MachineOperand::isRenamable function and how it is set and maintained. Change isRenamable to check the operand's opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of relying on it being consistently reflected in the IsRenamable bit setting. Clear the IsRenamable bit when changing an operand's register value. Remove target code that was clearing the IsRenamable bit when changing registers/opcodes now that this is done conservatively by default. Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in one place covering all opcodes that have constant pipe read limit restrictions. Reviewers: qcolombet, MatzeB Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D43042 llvm-svn: 325931
* [DAGCOmbine] Ensure that (brcond (setcc ...)) is handled in a canonical manner.Amaury Sechet2018-02-231-75/+67
| | | | | | | | | | | | | | | Summary: There are transformation that change setcc into other constructs, and transform that try to reconstruct a setcc from the brcond condition. Depending on what order these transform are done, the end result differs. Most of the time, it is preferable to get a setcc as a brcond argument (and this is why brcond try to recreate the setcc in the first place) so we ensure this is done every time by also doing it at the setcc level when the only user is a brcond. Reviewers: spatel, hfinkel, niravd, craig.topper Subscribers: nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D41235 llvm-svn: 325892
* [TargetLowering] Rename isCondCodeLegal to isCondCodeLegalOrCustom. Add real ↵Craig Topper2018-02-222-13/+12
| | | | | | | | | | | | | | | | isCondCodeLegal. Update callers to use one or the other. isCondCodeLegal internally checked Legal or Custom which is misleading. Though no targets set any cond code action to Custom today. So I've renamed isCondCodeLegal to isCondCodeLegalOrCustom and added a real isCondCodeLegal that only checks Legal. I've changed legalization code to use isCondCodeLegalOrCustom and left things reachable via DAG combine as isCondCodeLegal. I've also changed some places that called getCondCodeAction and compared to Legal to just use isCondCodeLegal. I'm looking at trying to keep SETCC all the way to isel for the AVX512 integer comparisons and I suspect I'll need to make some condition codes Custom to stop DAG combine from changing things post LegalizeOps. Prior to this only Expand stopped DAG combine, but that causes LegalizeOps to try to swap operands or invert rather than calling our Custom handler. Differential Revision: https://reviews.llvm.org/D43607 llvm-svn: 325829
* Revert "[DebugInfo][FastISel] Fix dropping dbg.value()"Sander de Smalen2018-02-221-1/+1
| | | | | | | | | This patch reverts r325440 and r325438 because it triggers an assertion in SelectionDAGBuilder.cpp. Also having debug enabled may unintentionally affect code-gen. The patch is reverted until we find a better solution. llvm-svn: 325825
* [SelectionDAG] Move matchUnaryPredicate/matchBinaryPredicate into ↵Simon Pilgrim2018-02-222-62/+58
| | | | | | | | | | SelectionDAGNodes.h This allows us to improve vector constant matching in more DAG code (backends, TargetLowering etc.). Differential Revision: https://reviews.llvm.org/D43466 llvm-svn: 325815
* [DEBUGINFO] Do not output labels for empty macinfo sections.Alexey Bataev2018-02-221-2/+5
| | | | | | | | | | | | | | Summary: If there is no debug info for macros, do not emit labels for empty macinfo sections. Reviewers: probinson, echristo Subscribers: aprantl, llvm-commits, JDevlieghere Differential Revision: https://reviews.llvm.org/D43589 llvm-svn: 325803
* [DAGCombiner] Add two calls to isVector before making calls to ↵Craig Topper2018-02-221-4/+5
| | | | | | | | | | getVectorElementType/getVectorNumElements to avoid an assert. We looked through a BITCAST, but the bitcast might be a from a scalar type rather than a vector. I don't have a test case. I stumbled onto it while prototyping another change that isn't ready yet. llvm-svn: 325750
* [PBQP] Fix PR33038 by pruning empty intervals in initializeGraph.Lang Hames2018-02-201-11/+27
| | | | | | | | Spilling may cause previously non-empty intervals (both for the spilled vreg and others) to become empty. Moving the pruning into initializeGraph catches these cases and fixes PR33038. llvm-svn: 325632
* [SelectionDAG] Support known true/false SimplifySetCC cases for comparing ↵Craig Topper2018-02-201-58/+87
| | | | | | | | | | | | | | against vector splats of constants. This is split off from D42948 and includes just the cases that constant fold to true or false. It also includes some refactoring to keep predicate checks together. This supports things like (setcc uge X, 0) -> true Differential Revision: https://reviews.llvm.org/D43489 llvm-svn: 325627
* [SelectionDAG] Add LegalTypes flag to getShiftAmountTy. Use it to unify and ↵Craig Topper2018-02-203-19/+15
| | | | | | | | | | | | | | | | | | simplify DAGCombiner and simplifySetCC code and fix a bug. DAGCombiner and SimplifySetCC both use getPointerTy for shift amounts pre-legalization. DAGCombiner uses a single helper function to hide this. SimplifySetCC does it in multiple places. This patch adds a defaulted parameter to getShiftAmountTy that can make it return getPointerTy for scalar types. Use this parameter to simplify the SimplifySetCC and DAGCombiner. Additionally, there were two places in SimplifySetCC that were creating shifts using the target's preferred shift amount pre-legalization. If the target uses a narrow type and the type is illegal, this can cause SimplfiySetCC to create a shift with an amount that can't represent all possible shift values for the type. To fix this we should use pointer type there too. Alternatively we could make getScalarShiftAmountTy for each target return a safe value for large types as proposed in D43445. And maybe we should still do that, but fixing the SimplifySetCC code keeps other targets from tripping over this in the future. Fixes PR36250. Differential Revision: https://reviews.llvm.org/D43449 llvm-svn: 325602
* [DEBUGINFO] Add support for emission of the inlined strings.Alexey Bataev2018-02-203-0/+21
| | | | | | | | | | | | | | Summary: Patch adds an option for emission of inlined strings rather than .debug_str section. Reviewers: echristo, jlebar Subscribers: eraman, llvm-commits, JDevlieghere Differential Revision: https://reviews.llvm.org/D43390 llvm-svn: 325583
* [VectorLegalizer] Fix uint64_t typo in ExpandUINT_TO_FLOAT (PR36391)Simon Pilgrim2018-02-201-1/+1
| | | | | | | | ExpandUINT_TO_FLOAT can accept vXi32 or vXi64 inputs, so we need to use a uint64_t shift to generate the 2^(BW/2) constant. No test case unfortunately as no upstream target uses this, but its affecting a downstream target. llvm-svn: 325578
* Report fatal error in the case of out of memorySerge Pavlov2018-02-203-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the second part of recommit of r325224. The previous part was committed in r325426, which deals with C++ memory allocation. Solution for C memory allocation involved functions `llvm::malloc` and similar. This was a fragile solution because it caused ambiguity errors in some cases. In this commit the new functions have names like `llvm::safe_malloc`. The relevant part of original comment is below, updated for new function names. Analysis of fails in the case of out of memory errors can be tricky on Windows. Such error emerges at the point where memory allocation function fails, but manifests itself when null pointer is used. These two points may be distant from each other. Besides, next runs may not exhibit allocation error. In some cases memory is allocated by a call to some of C allocation functions, malloc, calloc and realloc. They are used for interoperability with C code, when allocated object has variable size and when it is necessary to avoid call of constructors. In many calls the result is not checked for null pointer. To simplify checks, new functions are defined in the namespace 'llvm': `safe_malloc`, `safe_calloc` and `safe_realloc`. They behave as corresponding standard functions but produce fatal error if allocation fails. This change replaces the standard functions like 'malloc' in the cases when the result of the allocation function is not checked for null pointer. Finally, there are plain C code, that uses malloc and similar functions. If the result is not checked, assert statement is added. Differential Revision: https://reviews.llvm.org/D43010 llvm-svn: 325551
* [SelectionDAG] ComputeKnownBits - add support for SMIN+SMAX clamp patternsSimon Pilgrim2018-02-191-5/+32
| | | | | | | | | | If we have a clamp pattern, SMIN(SMAX(X, LO),HI) or SMAX(SMIN(X, HI),LO) then we can deduce that the number of signbits (zeros/ones) will be at least the minimum of the LO and HI constants. ComputeKnownBits equivalent of D43338. Differential Revision: https://reviews.llvm.org/D43463 llvm-svn: 325521
* [CodeGen] Refactor AppleAccelTablePavel Labath2018-02-193-155/+242
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This commit separates the abstract accelerator table data structure from the code for writing out an on-disk representation of a specific accelerator table format. The idea is that former (now called AccelTable<T>) can be reused for the DWARF v5 accelerator tables as-is, without any further customizations. Some bits of the emission code (now living in the EmissionContext class) can be reused for DWARF v5 as well, but the subtle differences in the layout of various subtables mean the sharing is not always possible. (Also, the individual emit*** functions are fairly simple so there's a tradeoff between making a bigger general-purpose function, and two smaller targeted functions.) Another advantage of this setup is that more of the serialization logic can be hidden in the .cpp file -- I have moved declarations of the header and all the emission functions there. Reviewers: JDevlieghere, aprantl, probinson, dblaikie Subscribers: echristo, clayborg, vleschuk, llvm-commits Differential Revision: https://reviews.llvm.org/D43285 llvm-svn: 325516
* [CodeGen] Fix tests breaking after r325505Francis Visoiu Mistrih2018-02-191-2/+0
| | | | llvm-svn: 325512
* Revert "[CodeGen] Move printing '\n' from MachineInstr::print to ↵Francis Visoiu Mistrih2018-02-194-13/+8
| | | | | | | | MachineBasicBlock::print" This reverts commit r324681. llvm-svn: 325505
* Fix Wparentheses warning. NFCISimon Pilgrim2018-02-171-1/+1
| | | | llvm-svn: 325451
* [SelectionDAG] ComputeNumSignBits - add support for SMIN+SMAX clamp patternsSimon Pilgrim2018-02-171-1/+26
| | | | | | | | | | If we have a clamp pattern, SMIN(SMAX(X, LO),HI) or SMAX(SMIN(X, HI),LO) then we can deduce that the number of signbits will be at least the minimum of the LO and HI constants. I haven't bothered with the UMIN/UMAX equivalent as (1) we don't have any current use cases and (2) I wonder if we'd be better off immediately falling back for ComputeKnownBits for UMIN/UMAX which already has optimization patterns useful for unsigned cases. Differential Revision: https://reviews.llvm.org/D43338 llvm-svn: 325450
* [SelectionDAG] SimplifyDemandedVectorElts - add support for VECTOR_INSERT_ELTSimon Pilgrim2018-02-171-0/+34
| | | | | | Differential Revision: https://reviews.llvm.org/D43431 llvm-svn: 325449
* [DebugInfo][FastISel] Fix dropping dbg.value()Sander de Smalen2018-02-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Summary: https://llvm.org/PR36263 shows that when compiling at -O0 a dbg.value() instruction (that remains from an original dbg.declare()) is dropped by FastISel. Since FastISel selects instructions by iterating a basic block backwards, it drops the dbg.value if one of its operands is not yet instantiated by a previously selected instruction. Instead of calling 'lookUpRegForValue()' we can call 'getRegForValue()' instead that will insert a placeholder for the operand to be filled in when continuing the instruction selection. Reviewers: aprantl, dblaikie, probinson Reviewed By: aprantl Subscribers: llvm-commits, dstenb, JDevlieghere Differential Revision: https://reviews.llvm.org/D43386 llvm-svn: 325438
* [AArch64] Implement dynamic stack probing for windowsMartin Storsjo2018-02-171-0/+4
| | | | | | | | | This makes sure that alloca() function calls properly probe the stack as needed. Differential Revision: https://reviews.llvm.org/D42356 llvm-svn: 325433
* [DAGCombiner] Remove simplifyShuffleMask - now handled more generally by ↵Simon Pilgrim2018-02-171-35/+0
| | | | | | SimplifyDemandedVectorElts. llvm-svn: 325429
* [DebugInfo] Removed assert on missing CountVarDIESander de Smalen2018-02-171-7/+2
| | | | | | | | | | | | | | | | | | | | Summary: The assert for a DISubrange's CountVarDIE to be available fails when the dbg.value() has been optimized away for any reason. Having the assert for that is a little heavy, so instead removing it now in favor of not generating the 'count' expression. Addresses http://llvm.org/PR36263 . Reviewers: aprantl, dblaikie, probinson Reviewed By: aprantl Subscribers: JDevlieghere, llvm-commits, dstenb Differential Revision: https://reviews.llvm.org/D43387 llvm-svn: 325427
* Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding"Quentin Colombet2018-02-172-210/+1
| | | | | | | | | | | | | | | | | This reverts commit r323991. This commit breaks target that don't model all the register constraints in TableGen. So far the workaround was to set the hasExtraXXXRegAllocReq, but it proves that it doesn't cover all the cases. For instance, when mutating an instruction (like in the lowering of COPYs) the isRenamable flag is not properly updated. The same problem will happen when attaching machine operand from one instruction to another. Geoff Berry is working on a fix in https://reviews.llvm.org/D43042. llvm-svn: 325421
* [DAG, X86] Revert r324797, r324491, and r324359.Chandler Carruth2018-02-171-79/+215
| | | | | | | | | | | | Sadly, r324359 caused at least PR36312. There is a patch out for review but it seems to be taking a bit and we've already had these crashers in tree for too long. We're hitting this PR in real code now and are blocked on shipping new compilers as a consequence so I'm reverting us back to green. Sorry for the churn due to the stacked changes that I had to revert. =/ llvm-svn: 325420
* Fix signed/unsigned comparison warning. NFCI.Simon Pilgrim2018-02-161-1/+1
| | | | llvm-svn: 325363
* Fix signed/unsigned comparison warning. NFCI.Simon Pilgrim2018-02-161-3/+3
| | | | llvm-svn: 325359
* [SelectionDAG] Enable SimplifyDemandedVectorElts support for simplifying ↵Simon Pilgrim2018-02-161-0/+25
| | | | | | | | | | shuffle masks Based off the DemandedElts mask the and UNDEF elements returned from the SimplifyDemandedVectorElts calls to the shuffle operands, we can attempt to simplify the shuffle mask. I had to be very conservative here as accepting post-legalized shuffle masks could cause problems for targets that legalize UNDEF mask elements back to inrange values (PowerPC), similarly combining to identity shuffle masks could cause too much UNDEF information to disappear for later combines. llvm-svn: 325354
* [SelectionDAG] Add initial SimplifyDemandedVectorElts support for ↵Simon Pilgrim2018-02-161-0/+20
| | | | | | | | simplifying VSELECT operands This just adds a basic pass through - we can add constant selection mask handling in a future patch to fully match InstCombine. llvm-svn: 325338
* [LegalizeDAG] Fix legalization of SETCCMikhail Maltsev2018-02-161-1/+1
| | | | | | | | | | | | | | | | | | | Summary: Currently when expanding a SETCC node into a SELECT_CC, LLVM uses an incorrect type for determining BooleanContent of the result. This patch fixes the issue. Fixes PR36079. Reviewers: rogfer01, javed.absar, efriedma Reviewed By: efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D43282 llvm-svn: 325325
* [DAGCombiner] Call ExtendUsesToFormExtLoad in (zext (and (load)))->(and ↵Craig Topper2018-02-151-13/+14
| | | | | | | | | | | | | | (zextload)) even when the and does not have multiple uses Same for the sign extend case. Currently we check for multiple uses on the binop. Then we call ExtendUsesToFormExtLoad to capture SetCCs that use the load. So we only end up finding any setccs when the and has additional uses and the load is used by a setcc. I don't think the and having multiple uses is relevant here. I think we should only be checking for the load having multiple uses. This changes an NVPTX test because we now find that the load has a second use by a truncate, but ExtendUsesToFormExtLoad only looks at setccs it can extend. All other operations just check isTruncateFree. Maybe we should allow widening of an existing truncate even if its not free? Differential Revision: https://reviews.llvm.org/D43063 llvm-svn: 325289
* [CodeGen] Separate MBB metadata from instructions in -debug printingFrancis Visoiu Mistrih2018-02-151-1/+9
| | | | | | | Add an empty line after 'liveins:', 'successors:', or '; predecessors:', the one that ends up to be the last one. llvm-svn: 325258
* [SelectionDAG] Pull out repeated Op.getOpcode(). NFCI.Simon Pilgrim2018-02-151-6/+7
| | | | llvm-svn: 325253
* [CodeGen] Print irreducible loop header weight as a MIR commentFrancis Visoiu Mistrih2018-02-151-3/+2
| | | | | | Prefix it with '; ' to make it more MIR-compatible. llvm-svn: 325251
* [DebugInfo] Accept enumeration types without underlying integer type present inMomchil Velikov2018-02-151-5/+5
| | | | | | | | | | debug info metadata ... when generating DWARF. Differential Revision: https://reviews.llvm.org/D43304 llvm-svn: 325234
* [SelectionDAG] Add initial implementation of ↵Simon Pilgrim2018-02-152-91/+238
| | | | | | | | | | | | TargetLowering::SimplifyDemandedVectorElts This is mainly a move of simplifyShuffleOperands from DAGCombiner::visitVECTOR_SHUFFLE to create a more general purpose TargetLowering::SimplifyDemandedVectorElts implementation. Further features can be moved/added in future patches. Differential Revision: https://reviews.llvm.org/D42896 llvm-svn: 325232
* Revert r325224 "Report fatal error in the case of out of memory"Serge Pavlov2018-02-153-5/+4
| | | | | | It caused fails on some buildbots. llvm-svn: 325227
* Report fatal error in the case of out of memorySerge Pavlov2018-02-153-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Analysis of fails in the case of out of memory errors can be tricky on Windows. Such error emerges at the point where memory allocation function fails, but manifests itself when null pointer is used. These two points may be distant from each other. Besides, next runs may not exhibit allocation error. Usual programming practice does not require checking result of 'operator new' because it throws 'std::bad_alloc' in the case of allocation error. However, LLVM is usually built with exceptions turned off, so 'new' can return null pointer. This change installs custom new handler, which causes fatal error in the case of out of memory. The handler is installed automatically prior to call to 'main' during construction of a static object defined in 'lib/Support/ErrorHandling.cpp'. If the application does not use this file, the handler may be installed manually by a call to 'llvm::install_out_of_memory_new_handler', declared in 'include/llvm/Support/ErrorHandling.h". There are calls to C allocation functions, malloc, calloc and realloc. They are used for interoperability with C code, when allocated object has variable size and when it is necessary to avoid call of constructors. In many calls the result is not checked against null pointer. To simplify checks, new functions are defined in the namespace 'llvm' with the same names as these C function. These functions produce fatal error if allocation fails. User should use 'llvm::malloc' instead of 'std::malloc' in order to use the safe variant. This change replaces 'std::malloc' in the cases when the result of allocation function is not checked against null pointer. Finally, there are plain C code, that uses malloc and similar functions. If the result is not checked, assert statements are added. Differential Revision: https://reviews.llvm.org/D43010 llvm-svn: 325224
* (NFC)[MachineCombiner] Improve debug output.Andrew V. Tischenko2018-02-151-28/+53
| | | | llvm-svn: 325217
* [CodeGen] Print predecessors, successors, then liveins in -debug printingFrancis Visoiu Mistrih2018-02-141-17/+18
| | | | | | | | Reorder them to match MIR. Predecessors are only comments, and they're not usually printed in MIR. llvm-svn: 325166
* GlobalISel: Add templated functions and pattern matcher support for some ↵Volkan Keles2018-02-141-11/+7
| | | | | | | | | | | | | | | | | | more opcodes Summary: This patch adds templated functions to MachineIRBuilder for some opcodes and adds pattern matcher support for G_AND and G_OR. Reviewers: aditya_nandakumar Reviewed By: aditya_nandakumar Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D43309 llvm-svn: 325162
* Pass a reference to a module to the bitcode writer.Rafael Espindola2018-02-141-2/+2
| | | | | | | This simplifies most callers as they are already using references or std::unique_ptr. llvm-svn: 325155
* [RegisterClassInfo] Invalidate the register pressure set limit cache when ↵Craig Topper2018-02-141-4/+5
| | | | | | | | | | | | | | reserved regs or callee saved regs change Previously we only invalidated the pressure set limit cached when the TargetRegisterInfo pointer changes. But as reserved regs and callee saved regs are used as part of calculating the limits we should invalidate when those change too. I encountered this when reverting a patch from the 6.0 branch. One of the x86 test files had a function that used rbp as a frame pointer, making it reserved. It was followed by another function which didn't use rbp but had the same TRI so the pressure set limit cache was not invalidated. If i removed the function that used rbp as a frame pointer from the file, the remaining function then got a different register pressure limit for the GR16 pressure set. This caused the machine scheduler to change the scheduling for the function. This was an unexpected change from just deleting a function. I don't have a test case for trunk because the particular x86 test case is different enough from the 6.0 branch to not be affected now. Differential Revision: https://reviews.llvm.org/D43274 llvm-svn: 325153
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