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* [MC] Undo spurious commit added into r331052.Nirav Dave2018-04-271-3/+0
| | | | llvm-svn: 331055
* [MC] Provide default value for IsResolved.Nirav Dave2018-04-271-0/+3
| | | | llvm-svn: 331052
* [MC] Modify MCAsmStreamer to always build MCAssembler. NFCI.Nirav Dave2018-04-271-6/+6
| | | | llvm-svn: 331048
* Revert "Fix a bug that prevents global variables from having a DW_OP_deref."Adrian Prantl2018-04-261-3/+2
| | | | | | This reverts commit r3309704 while investigating bot breakage. llvm-svn: 330993
* [GlobalISel] Reporting rules covered as part of the InstructionSelect's ↵Roman Tereshin2018-04-261-0/+6
| | | | | | | | | | | | | debug-only printing The main goal of this change is to make it much easier to track which rules are actually covered by Testgen'erated regression tests. Reviewers: aemerson, dsanders Differential Revision: https://reviews.llvm.org/D46095 llvm-svn: 330988
* DAG: Fix not legalizing vector fcanonicalizesMatt Arsenault2018-04-261-0/+1
| | | | | | If an fcanoncialize was done on a vector type that was legal, llvm-svn: 330981
* Fix a bug that prevents global variables from having a DW_OP_deref.Adrian Prantl2018-04-261-2/+3
| | | | | | | | | | | For local variables the first DW_OP_deref is consumed by turning the location kind into a memeory location, but that only makes sense for values that are in a register to begin with, which cannot happen for global variables that are attached to a symbol. rdar://problem/39741860 llvm-svn: 330970
* [GlobalMerge] Fix a typoHaicheng Wu2018-04-261-1/+1
| | | | | | now => know llvm-svn: 330965
* [DAGCombiner] limit ftrunc optimizations with function attributeSanjay Patel2018-04-261-0/+8
| | | | | | | | | | As noted, the attribute name is subject to change once we have the clang side implemented, but it's clear that we need some kind of attribute-based predication here based on the discussion for: rL330437 llvm-svn: 330951
* [DAGCombiner] refactor FP->int->FP folds; NFCSanjay Patel2018-04-261-16/+26
| | | | | | | | | | | | As discussed in the post-review comments for rL330437, we need to guard this fold to allow existing code to keep working with the undefined behavior that they've come to rely on. That would mean duplicating more code than we already have, so let's fix that first. llvm-svn: 330947
* [MIR] Add support for debug metadata for fixed stack objectsFrancis Visoiu Mistrih2018-04-252-17/+28
| | | | | | | | | | | | | | | Debug var, expr and loc were only supported for non-fixed stack objects. This patch adds the following fields to the "fixedStack:" entries, and renames the ones from "stack:" to: * debug-info-variable * debug-info-expression * debug-info-location Differential Revision: https://reviews.llvm.org/D46032 llvm-svn: 330859
* [DAGCombiner][X86] When promoting loads don't use ZEXTLOAD even its legalCraig Topper2018-04-241-8/+4
| | | | | | | | | | | | We were previously prefering ZEXTLOAD over EXTLOAD if it is legal. This triggers during X86's promotion of i16->i32. Not sure about other targets. Using ZEXTLOAD can prevent folding it to SEXTLOAD later if we were to promote a sign extended operand like we would need for SRA. However, X86 doesn't currently promote i16 SRA. I was looking into doing that which is how I found this issue. This is also blocking our ability to fold 4 byte aligned EXTLOADs with "loadi32". This is what caused most of the test changes here. Differential Revision: https://reviews.llvm.org/D45585#inline-402825 llvm-svn: 330781
* [X86] Account for partial stack slot spills (PR30821)Warren Ristow2018-04-241-3/+7
| | | | | | | | | | | | | | | | | | | | | | | Previously, _any_ store or load instruction was considered to be operating on a spill if it had a frameindex as an operand, and thus was fair game for optimisations such as "StackSlotColoring". This usually works, except on architectures where spills can be partially restored, for example on X86 where a spilt vector can have a single component loaded (zeroing the rest of the target register). This can be mis-interpreted and the zero extension unsoundly eliminated, see pr30821. To avoid this, this commit optionally provides the caller to isLoadFromStackSlot and isStoreToStackSlot with the number of bytes spilt/loaded by the given instruction. Optimisations can then determine that a full spill followed by a partial load (or vice versa), for example, cannot necessarily be commuted. Patch by Jeremy Morse! Differential Revision: https://reviews.llvm.org/D44782 llvm-svn: 330778
* [CodeGen] Print user-friendly debug locations as MI commentsFrancis Visoiu Mistrih2018-04-241-1/+14
| | | | | | | | | | | | If available, print the file, line and column of the DebugLoc attached to the MachineInstr: MOV16mr $rbp, 1, $noreg, -112, $noreg, killed renamable $ax, debug-location !56 :: (store 2 into %ir.._value12); stepping.swift:10:17 renamable $edx = MOVZX32rm16 $rbp, 1, $noreg, -112, $noreg, debug-location !62 :: (dereferenceable load 2 from %ir.._value13); stepping.swift:10:17 Differential Revision: https://reviews.llvm.org/D45992 llvm-svn: 330709
* Correct dwarf unwind information in function epiloguePetar Jovanovic2018-04-245-12/+368
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch aims to provide correct dwarf unwind information in function epilogue for X86. It consists of two parts. The first part inserts CFI instructions that set appropriate cfa offset and cfa register in emitEpilogue() in X86FrameLowering. This part is X86 specific. The second part is platform independent and ensures that: * CFI instructions do not affect code generation (they are not counted as instructions when tail duplicating or tail merging) * Unwind information remains correct when a function is modified by different passes. This is done in a late pass by analyzing information about cfa offset and cfa register in BBs and inserting additional CFI directives where necessary. Added CFIInstrInserter pass: * analyzes each basic block to determine cfa offset and register are valid at its entry and exit * verifies that outgoing cfa offset and register of predecessor blocks match incoming values of their successors * inserts additional CFI directives at basic block beginning to correct the rule for calculating CFA Having CFI instructions in function epilogue can cause incorrect CFA calculation rule for some basic blocks. This can happen if, due to basic block reordering, or the existence of multiple epilogue blocks, some of the blocks have wrong cfa offset and register values set by the epilogue block above them. CFIInstrInserter is currently run only on X86, but can be used by any target that implements support for adding CFI instructions in epilogue. Patch by Violeta Vukobrat. Differential Revision: https://reviews.llvm.org/D42848 llvm-svn: 330706
* [CodeGen] Do not allow opt-bisect-limit to skip ScalarizeMaskedMemIntrin.Andrei Elovikov2018-04-241-3/+0
| | | | | | | | | | | | | | | | | Summary: The pass is supposed to scalarize such intrinsics if the target does not support them natively, so if the scalarization does not happen instruction selection crashes due to inability to lower these intrinsics. Reviewers: andrew.w.kaylor, craig.topper Reviewed By: andrew.w.kaylor Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45947 llvm-svn: 330700
* [DAGCombiner] Unfold scalar masked merge if profitableRoman Lebedev2018-04-231-0/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is [[ https://bugs.llvm.org/show_bug.cgi?id=37104 | PR37104 ]]. [[ https://bugs.llvm.org/show_bug.cgi?id=6773 | PR6773 ]] will introduce an IR canonicalization that is likely bad for the end assembly. Previously, `andl`+`andn`/`andps`+`andnps` / `bic`/`bsl` would be generated. (see `@out`) Now, they would no longer be generated (see `@in`). So we need to make sure that they are still generated. If the mask is constant, we do nothing. InstCombine should have unfolded it. Else, i use `hasAndNot()` TLI hook. For now, only handle scalars. https://rise4fun.com/Alive/bO6 ---- I *really* don't like the code i wrote in `DAGCombiner::unfoldMaskedMerge()`. It is super fragile. Is there something like IR Pattern Matchers for this? Reviewers: spatel, craig.topper, RKSimon, javed.absar Reviewed By: spatel Subscribers: andreadb, courbet, kristof.beyls, javed.absar, rengolin, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D45733 llvm-svn: 330646
* [SelectionDAG] Dump debug locs in SDNodesVedant Kumar2018-04-231-0/+4
| | | | | | | | | This helps debug issues where selection-dag assigns the wrong location to an instruction. Differential Revision: https://reviews.llvm.org/D45913 llvm-svn: 330618
* StackSlotColoring: Fix missing skipFunction checkMatt Arsenault2018-04-231-0/+3
| | | | llvm-svn: 330606
* [SelectionDAG] Refactor lowering of atomic memory intrinsics.Daniel Neilson2018-04-232-91/+150
| | | | | | | | | | | Summary: This just refactors the lowering of the atomic memory intrinsics to more closely match the code patterns used in the lowering of the non-atomic memory intrinsics. Specifically, we encapsulate the lowering in SelectionDAG::getAtomicMem*() functions rather than embedding the code directly in the SelectionDAGBuilder code. llvm-svn: 330603
* [AArch64] Don't crash trying to resolve __stack_chk_guard.Eli Friedman2018-04-211-2/+5
| | | | | | | | | | In certain cases, the compiler might try to merge __stack_chk_guard with another global variable. (Or someone could theoretically define __stack_chk_guard as an alias.) In that case, make sure we don't crash. Differential Revision: https://reviews.llvm.org/D45746 llvm-svn: 330495
* Remove unused argument from emitModuleMetadata.Eric Christopher2018-04-202-7/+7
| | | | | | NFCI. llvm-svn: 330470
* [DAGCombine] (float)((int) f) --> ftrunc (PR36617)Sanjay Patel2018-04-201-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was originally committed at rL328921 and reverted at rL329920 to investigate failures in Chrome. This time I've added to the ReleaseNotes to warn users of the potential of exposing UB and let me repeat that here for more exposure: Optimization of floating-point casts is improved. This may cause surprising results for code that is relying on undefined behavior. Code sanitizers can be used to detect affected patterns such as this: int main() { float x = 4294967296.0f; x = (float)((int)x); printf("junk in the ftrunc: %f\n", x); return 0; } $ clang -O1 ftrunc.c -fsanitize=undefined ; ./a.out ftrunc.c:5:15: runtime error: 4.29497e+09 is outside the range of representable values of type 'int' junk in the ftrunc: 0.000000 Original commit message: fptosi / fptoui round towards zero, and that's the same behavior as ISD::FTRUNC, so replace a pair of casts with the equivalent node. We don't have to account for special cases (NaN, INF) because out-of-range casts are undefined. Differential Revision: https://reviews.llvm.org/D44909 llvm-svn: 330437
* Move a dump() implementation out of line.Amara Emerson2018-04-201-0/+11
| | | | | | Fixes some link issues. llvm-svn: 330384
* [MachineOutliner] NFC: Move EnableLinkOnceODROutlining into MachineOutliner.cppJessica Paquette2018-04-192-10/+20
| | | | | | | | | This moves the EnableLinkOnceODROutlining flag from TargetPassConfig.cpp into MachineOutliner.cpp. It also removes OutlineFromLinkOnceODRs from the MachineOutliner constructor. This is now handled by the moved command-line flag. llvm-svn: 330373
* [if-converter] Handle BBs that terminate in ret during diamond conversionKrzysztof Parzyszek2018-04-191-11/+28
| | | | | | | | | | This fixes https://llvm.org/PR36825. Original patch by Valentin Churavy (D45218). Differential Revision: https://reviews.llvm.org/D45731 llvm-svn: 330345
* [DEBUG] Initial adaptation of NVPTX target for debug info emission.Alexey Bataev2018-04-181-7/+15
| | | | | | | | | | | | | | | Summary: Patch adds initial emission of the debug info for NVPTX target. Currently, only .file and .loc directives are emitted, everything else is commented out to not break the compilation of Cuda. Reviewers: echristo, jlebar, tra, jholewinski Subscribers: mgorny, aprantl, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D41827 llvm-svn: 330271
* [AMDGPU] Fix issues for backend divergence trackingDavid Stuttard2018-04-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: A change to use divergence analysis in the AMDGPU backend was getting formal arguments incorrect (not tagged as divergent) unless they were VGPR0, VGPR1 or VGPR2 For graphics shaders it is possible to have more than these passed in as VGPR Modified the checking code to check for any VGPR registers passed in as formal arguments. Also, some intrinsics that are sources of divergence may have been lowered during instruction selection and are missed on subsequent calls to isSDNodeSourceOfDivergence - added the relevant AMDGPUISD checks as well. Finally, the FunctionLoweringInfo tracks virtual registers that are live across basic block boundaries. This is used to check for divergence of CopyFromRegister registers using the DivergenceAnalysis analysis. For multiple blocks the lazily evaluated inverted map VirtReg2Value was not cleared when the ValueMap map was. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D45372 Change-Id: I112f3bd6dfe0f62e63ce9b43b893982778e4bee3 llvm-svn: 330257
* [CodeGen/Dwarf] Make debug_names compatible with split-dwarfPavel Labath2018-04-183-7/+17
| | | | | | | | | | | | | | | | | | Summary: Previously we crashed for the combination of the two features because we tried to reference the dwo CU from the main object file. The fix consists of two items: - reference the skeleton CU from the name index (the consumer is expected to use the skeleton CU to find the real data). - use the main object file string pool for the strings in the index Reviewers: JDevlieghere, aprantl, dblaikie Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45566 llvm-svn: 330249
* [XRay] Typed event logging intrinsicKeith Wyss2018-04-173-0/+72
| | | | | | | | | | | | | | | | | | | | | Summary: Add an LLVM intrinsic for type discriminated event logging with XRay. Similar to the existing intrinsic for custom events, but also accepts a type tag argument to allow plugins to be aware of different types and semantically interpret logged events they know about without choking on those they don't. Relies on a symbol defined in compiler-rt patch D43668. I may wait to submit before I can see demo everything working together including a still to come clang patch. Reviewers: dberris, pelikan, eizan, rSerge, timshen Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45633 llvm-svn: 330219
* Fix incorrect choice of callee-saved registers save/restore pointsMomchil Velikov2018-04-171-2/+14
| | | | | | | | Make the shrink wrapping pass pay attention to uses/defs of the stack pointer. Differential revision: https://reviews.llvm.org/D45524 llvm-svn: 330183
* [DAGCombiner] Fix for oss-fuzz bugGerolf Hoflehner2018-04-171-1/+2
| | | | llvm-svn: 330178
* [CodeView] Initial support for emitting S_THUNK32 symbols for compiler...Brock Wyma2018-04-162-1/+62
| | | | | | | | | | | When emitting CodeView debug information, compiler-generated thunk routines should be emitted using S_THUNK32 symbols instead of S_GPROC32_ID symbols so Visual Studio can properly step into the user code. This initial support only handles standard thunk ordinals. Differential Revision: https://reviews.llvm.org/D43838 llvm-svn: 330132
* [MIR-Canon] Adding ISA-Agnostic COPY Folding.Puyan Lotfi2018-04-161-0/+43
| | | | | | | | | | | | | | | | | Transforms the following: %vreg1234:gpr32 = COPY %42 %vreg1235:gpr32 = COPY %vreg1234 %vreg1236:gpr32 = COPY %vreg1235 $w0 = COPY %vreg1236 into: $w0 = COPY %42 Assuming %42 is also a gpr32 llvm-svn: 330113
* [NFC][MIR-Canon] clang-format cleanup of Mir Canonicalizer Pass.Puyan Lotfi2018-04-161-66/+60
| | | | llvm-svn: 330111
* [X86] Use APInt::isSubsetof instead of APInt::intersects to avoid a negation ↵Craig Topper2018-04-151-2/+2
| | | | | | of an APInt value. NFC llvm-svn: 330105
* [SelectionDAG][NFC] haveNoCommonBitsSet(): add FIXME notesRoman Lebedev2018-04-151-0/+2
| | | | | | As suggested in https://reviews.llvm.org/D45631#1068338 llvm-svn: 330102
* [MC] Moved all the remaining logic that computed instruction latency and ↵Andrea Di Biagio2018-04-152-37/+12
| | | | | | | | | | reciprocal throughput from TargetSchedModel to MCSchedModel. TargetSchedModel now always delegates to MCSchedModel the computation of instruction latency and reciprocal throughput. No functional change intended. llvm-svn: 330099
* [DAGCombiner, PowerPC] allow X - (fpext(-Y) --> X + fpext(Y) with multiple usesSanjay Patel2018-04-151-6/+6
| | | | | | | | | | | | | This is a transform that I limited in instcombine in rL329821 because it was creating more instructions in IR when the cast has multiple uses. But if the cast is free, then we can do the transform regardless of other uses because it improves the potential throughput of the calculation by removing a dependency on the fneg. Differential Revision: https://reviews.llvm.org/D45598 llvm-svn: 330098
* [PostRASink]Add register dependency check for implicit operandsJun Bum Lim2018-04-131-23/+103
| | | | | | | | | | | | | | | | Summary: This change extend the register dependency check for implicit operands in Copy instructions. Fixes PR36902. Reviewers: thegameg, sebpop, uweigand, jnspaulsson, gberry, mcrosier, qcolombet, MatzeB Reviewed By: thegameg Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D44958 llvm-svn: 330018
* [NFC] fix trivial typos in commentsHiroshi Inoue2018-04-131-1/+1
| | | | | | "the the" -> "the", "we we" -> "we", etc llvm-svn: 330006
* [DAGCombiner] simplify code; NFCSanjay Patel2018-04-121-3/+2
| | | | llvm-svn: 329964
* revert r328921 - [DAGCombine] (float)((int) f) --> ftrunc (PR36617)Sanjay Patel2018-04-121-18/+0
| | | | | | | This change is exposing UB in source code - as was warned/predicted. :) See D44909 for discussion. Reverting while we figure out how to fix things. llvm-svn: 329920
* [Pipeliner] Use std::stable_sort when ordering NodeSetsKrzysztof Parzyszek2018-04-121-1/+1
| | | | | | | | | | | There are cases when individual NodeSets can be equal with respect to the ordering criteria. Since they are stored in an ordered container, use stable_sort to preserve the relative order of equal NodeSets. This should remove non-determinism discovered by shuffling done in llvm::sort with expensive checks enabled. llvm-svn: 329915
* [CodeGen] Allow printing MachineMemOperands with less context in SDAGDumperFrancis Visoiu Mistrih2018-04-121-8/+21
| | | | | | | | | Don't assume SelectionDAG is non-null as the targets can use it with a null pointer. Differential Revision: https://reviews.llvm.org/D44611 llvm-svn: 329908
* [MachineScheduler] NFC refactoringJonas Paulsson2018-04-121-21/+25
| | | | | | | | | | | | | | | | This patch makes tryCandidate() virtual and some utility functions like tryLess(), tryGreater(), ... externally available (used to be static). This makes it possible for a target to derive a new MachineSchedStrategy from GenericScheduler and reuse most parts. It was necessary to wrap functions with the same names in AMDGPU/SIMachineScheduler in a local namespace. Review: Andy Trick, Florian Hahn https://reviews.llvm.org/D43329 llvm-svn: 329884
* [LegalizeTypes] Remove unnecessary type action check on the type of operand ↵Craig Topper2018-04-121-11/+5
| | | | | | | | 0 when promoting shift result type. NFC Operand 0 should have the same type of the result. So if the result type needs to be promoted, operand 0 needs to be promoted unconditionally. llvm-svn: 329883
* [NFC] fix trivial typos in documents and commentsHiroshi Inoue2018-04-121-1/+1
| | | | | | "is is" -> "is", "if if" -> "if", "or or" -> "or" llvm-svn: 329878
* CodeGen: Don't try to canonicalize Unix-style paths in CodeView debug info.Peter Collingbourne2018-04-111-0/+10
| | | | | | | | | Most importantly, we should not replace slashes with backslashes because that would invalidate the path. Differential Revision: https://reviews.llvm.org/D45473 llvm-svn: 329838
* [FastISel] Disable local value sinking by defaultReid Kleckner2018-04-111-1/+8
| | | | | | | | | | | | | | | | | | This is causing compilation timeouts on code with long sequences of local values and calls (i.e. foo(1); foo(2); foo(3); ...). It turns out that code coverage instrumentation is a great way to create sequences like this, which how our users ran into the issue in practice. Intel has a tool that detects these kinds of non-linear compile time issues, and Andy Kaylor reported it as PR37010. The current sinking code scans the whole basic block once per local value sink, which happens before emitting each call. In theory, local values should only be introduced to be used by instructions between the current flush point and the last flush point, so we should only need to scan those instructions. llvm-svn: 329822
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