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* Next round of earlyclobber handling. Approach theDale Johannesen2008-09-249-176/+38
| | | | | | | | | | RA problem by expanding the live interval of an earlyclobber def back one slot. Remove overlap-earlyclobber throughout. Remove earlyclobber bits and their handling from live internals. llvm-svn: 56539
* Refactor the logic for testing if an instruction is dead into aDan Gohman2008-09-241-37/+48
| | | | | | separate method. llvm-svn: 56531
* Set SetStore to false, to allow this pass to deleteDan Gohman2008-09-241-1/+2
| | | | | | dead loads. llvm-svn: 56529
* Add a method to MachineInstr for testing whether it makesDan Gohman2008-09-241-9/+30
| | | | | | any volatile memory references. llvm-svn: 56528
* Properly handle 'm' inline asm constraints. If a GV is being selected for ↵Evan Cheng2008-09-242-5/+25
| | | | | | the addressing mode, it requires the same logic for PIC relative addressing, etc. llvm-svn: 56526
* s/ParameterAttributes/Attributes/gDevang Patel2008-09-232-2/+0
| | | | llvm-svn: 56513
* Now that DeadMachineInstructionElim is basically workingDan Gohman2008-09-231-6/+0
| | | | | | | correctly, it's not necessary to explicitly remove registers from their use-def lists. llvm-svn: 56509
* Arrange for FastISel code to have access to the MachineModuleInfoDan Gohman2008-09-232-5/+10
| | | | | | object. This will be needed to support debug info. llvm-svn: 56508
* Track local physical register liveness. This is not the mostDan Gohman2008-09-231-3/+53
| | | | | | | efficient implementation possible, but it's pretty simple and good enough for the time being. llvm-svn: 56504
* Replace the LiveRegs SmallSet with a simple counter that keepsDan Gohman2008-09-232-23/+29
| | | | | | | track of the number of live registers, which is all the set was being used for. llvm-svn: 56498
* Add initial support for inserting last minute copies.Owen Anderson2008-09-231-28/+53
| | | | llvm-svn: 56485
* Fix the alignment of loads from constant pool entries when theDan Gohman2008-09-222-1/+7
| | | | | | | load address has an offset from the base of the constant pool entry. llvm-svn: 56479
* Livestacks really does preserve everything.Evan Cheng2008-09-221-2/+1
| | | | llvm-svn: 56476
* Instead of setPreservesAll, just mark them preseving machine loop info and ↵Evan Cheng2008-09-226-6/+12
| | | | | | machine dominators. llvm-svn: 56475
* Significant improvements to the logic for merging live intervals. This code ↵Owen Anderson2008-09-221-15/+53
| | | | | | | | | can't just use LI::MergeValueAsValue, as its behavior in the presence of overlapping ranges isn't what StrongPHIElimination wants. llvm-svn: 56472
* Make log, log2, log10, exp, exp2 use Expand byDale Johannesen2008-09-221-0/+12
| | | | | | default. llvm-svn: 56471
* Mark several codegen passes as preserving all analysis.Evan Cheng2008-09-228-8/+26
| | | | llvm-svn: 56469
* More refactoring. Yawn.Dale Johannesen2008-09-221-126/+43
| | | | llvm-svn: 56468
* Refactor FP intrinisic setup. Per review feedback.Dale Johannesen2008-09-221-117/+28
| | | | llvm-svn: 56456
* Per review feedback: Only performEvan Cheng2008-09-221-39/+27
| | | | | | | (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), c)) etc. when both "trunc" and "and" have single uses. llvm-svn: 56452
* Initial support for the CMake build system.Oscar Fuentes2008-09-223-0/+74
| | | | llvm-svn: 56419
* Add helper function to get a 32-bit floating point constant. No ↵Bill Wendling2008-09-221-189/+106
| | | | | | functionality change. llvm-svn: 56418
* Factor out code into HandleVirtRegDef, for consistency withDan Gohman2008-09-211-13/+12
| | | | | | | Handle{Virt,Phys}Reg{Def,Use}. Remove a redundant check for register zero, and redundant checks for isPhysicalRegister. llvm-svn: 56412
* Fetch the starting index of the block when assigning intervals. This gets ↵Owen Anderson2008-09-211-2/+2
| | | | | | | | live-in indices correct in the presence of things like EH labels. llvm-svn: 56410
* don't print GlobalAddressSDNode's with an offset of zero as "foo0".Chris Lattner2008-09-211-5/+6
| | | | llvm-svn: 56399
* Teach coalescer about earlyclobber bits.Dale Johannesen2008-09-202-2/+17
| | | | | | Check bits for preferred register. llvm-svn: 56384
* Fix PR2808. When regalloc runs out of register, it spill a physical register ↵Evan Cheng2008-09-201-1/+4
| | | | | | around the live interval being allocated. Do not continue to try to spill another register, just grab the physical register and move on. llvm-svn: 56381
* Continue after removing the current MI.Evan Cheng2008-09-191-0/+1
| | | | llvm-svn: 56372
* Refactor X86SelectConstAddr, folding it into X86SelectAddress. ThisDan Gohman2008-09-191-21/+15
| | | | | | | results in better code for globals. Also, unbreak the local CSE for GlobalValue stub loads. llvm-svn: 56371
* Make earlyclobber stuff work when virtual regsDale Johannesen2008-09-191-8/+26
| | | | | | have previously been assigned conflicting physreg. llvm-svn: 56364
* Re-materalized definition instructions may be dead. Whack them.Evan Cheng2008-09-192-7/+33
| | | | llvm-svn: 56352
* Remove AsmThatEarlyClobber etc. from LiveIntervalAnalysisDale Johannesen2008-09-193-73/+79
| | | | | | | and redo as linked list walk. Logic moved into RA. Per review feedback. llvm-svn: 56326
* Somehow RegAllocLinearScan is keeping two pointers to MachineRegisterInfo.Evan Cheng2008-09-181-8/+6
| | | | llvm-svn: 56314
* Don't consider instructions with implicit physical registerDan Gohman2008-09-181-1/+2
| | | | | | defs to be necessarily live. llvm-svn: 56310
* Add a new "fast" scheduler. This is currently basically just aDan Gohman2008-09-181-0/+654
| | | | | | | | | | | | | | | | copy of the BURRList scheduler, but with several parts ripped out, such as backtracking, online topological sort maintenance (needed by backtracking), the priority queue, and Sethi-Ullman number computation and maintenance (needed by the priority queue). As a result of all this, it generates somewhat lower quality code, but that's its tradeoff for running about 30% faster than list-burr in -fast mode in many cases. This is somewhat experimental. Moving forward, major pieces of this can be refactored with pieces in common with ScheduleDAGRRList.cpp. llvm-svn: 56307
* Add a bit to mark operands of asm's that conflictDale Johannesen2008-09-177-26/+140
| | | | | | | | | with an earlyclobber operand elsewhere. Propagate this bit and the earlyclobber bit through SDISel. Change linear-scan RA not to allocate regs in a way that conflicts with an earlyclobber. See also comments. llvm-svn: 56290
* Unallocatable registers do not have live intervals.Evan Cheng2008-09-171-1/+3
| | | | llvm-svn: 56287
* Don't worry about clobbering physical register defs that aren't used.Dan Gohman2008-09-171-0/+2
| | | | llvm-svn: 56281
* Add a new MachineInstr-level DCE pass. It is very simple, and is intended toDan Gohman2008-09-171-0/+99
| | | | | | be used with fast-isel. llvm-svn: 56268
* When converting a CopyFromReg to a copy instruction, use the register class ↵Evan Cheng2008-09-161-5/+24
| | | | | | of its uses to determine the right destination register class of the copy. This is important for targets where a physical register may belong to multiple register classes. llvm-svn: 56258
* Change SelectionDAG::getConstantPool to always set the alignment of theDan Gohman2008-09-162-7/+20
| | | | | | | | | | | | | | | | | | | | ConstantPoolSDNode, using the target's preferred alignment for the constant type. In LegalizeDAG, when performing loads from the constant pool, the ConstantPoolSDNode's alignment is used in the calls to getLoad and getExtLoad. This change prevents SelectionDAG::getLoad/getExtLoad from incorrectly choosing the ABI alignment for constant pool loads when Alignment == 0. The incorrect alignment is only a performance issue when ABI alignment does not equal preferred alignment (i.e., on x86 it was generating MOVUPS instead of MOVAPS for v4f32 constant loads when the default ABI alignment for 128bit vectors is forced to 1 byte.) Patch by Paul Redmond! llvm-svn: 56253
* Reverting r56249. On further investigation, this functionality isn't needed.Bill Wendling2008-09-166-59/+45
| | | | | | Apologies for the thrashing. llvm-svn: 56251
* Include the alignment value when displaying ConstantPoolSDNodes.Dan Gohman2008-09-161-0/+1
| | | | llvm-svn: 56250
* - Change "ExternalSymbolSDNode" to "SymbolSDNode".Bill Wendling2008-09-166-45/+59
| | | | | | | | | | - Add linkage to SymbolSDNode (default to external). - Change ISD::ExternalSymbol to ISD::Symbol. - Change ISD::TargetExternalSymbol to ISD::TargetSymbol These changes pave the way to allowing SymbolSDNodes with non-external linkage. llvm-svn: 56249
* Fix these comments to reflect current reality. Surprisingly,Dan Gohman2008-09-161-1/+2
| | | | | | | MachineConstantPool::getConstantPoolIndex actually expects a log2-encoded alignment. llvm-svn: 56248
* Don't take the time to CheckDAGForTailCallsAndFixThem when tail callsDan Gohman2008-09-162-4/+10
| | | | | | | are not enabled. Instead just omit the tail call flag when calls are created. llvm-svn: 56235
* Live intervals for live-in registers should begin at the beginning of a ↵Owen Anderson2008-09-151-7/+11
| | | | | | | | | basic block, not at the first instruction. Also, their valno's should have an unknown def. This has no effect currently, but was causing issues when StrongPHIElimination was enabled. llvm-svn: 56231
* Re-enable SelectionDAG CSE for calls. It matters in the case ofDan Gohman2008-09-151-6/+20
| | | | | | libcalls, as in this testcase on ARM. llvm-svn: 56226
* Correctly update kill infos after extending a live range and merge 2 val#'s; ↵Evan Cheng2008-09-151-3/+8
| | | | | | fix 56165 - do not mark val# copy field if the copy does not define the val#. llvm-svn: 56199
* adjust last patch per review feedbackDale Johannesen2008-09-141-3/+3
| | | | llvm-svn: 56194
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