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* Simplify the interference checking code a bit.Jakob Stoklund Olesen2011-08-122-112/+42
| | | | | | | This is possible now that we now longer provide an interface to iterate the interference overlaps. llvm-svn: 137397
* Remove the InterferenceResult class.Jakob Stoklund Olesen2011-08-111-32/+0
| | | | llvm-svn: 137381
* Eliminate the last use of InterferenceResult.Jakob Stoklund Olesen2011-08-112-63/+57
| | | | | | | | The Query class now holds two iterators instead of an InterferenceResult instance. The iterators are used as bookmarks for repeated collectInterferingVRegs calls. llvm-svn: 137380
* Remove more dead code.Jakob Stoklund Olesen2011-08-112-37/+3
| | | | | | | collectInterferingVRegs will be the primary function for interference checks. llvm-svn: 137354
* Privatize an unused part of the LiveIntervalUnion::Query interface.Jakob Stoklund Olesen2011-08-112-19/+13
| | | | | | No clients are iterating over interference overlaps. llvm-svn: 137350
* Remove some dead code.Jakob Stoklund Olesen2011-08-112-39/+0
| | | | | | | | The InterferenceResult iterator turned out to be less important than we thought it would be. LiveIntervalUnion clients want higher level information, like the list of interfering virtual registers. llvm-svn: 137346
* Plug a memory leak.Benjamin Kramer2011-08-111-3/+3
| | | | llvm-svn: 137321
* [AVX] When joining two XMM registers into a YMM register, make sure that theNadav Rotem2011-08-111-0/+32
| | | | | | | lower XMM register gets in first. This will allow the SUBREG pattern to elliminate the first vector insertion. llvm-svn: 137310
* fix PR10605 / rdar://9930964 by adding a pretty scary missed check.Chris Lattner2011-08-111-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | It's somewhat surprising anything works without this. Before we would compile the testcase into: test: # @test movl $4, 8(%rdi) movl 8(%rdi), %eax orl %esi, %eax cmpl $32, %edx movl %eax, -4(%rsp) # 4-byte Spill je .LBB0_2 now we produce: test: # @test movl 8(%rdi), %eax movl $4, 8(%rdi) orl %esi, %eax cmpl $32, %edx movl %eax, -4(%rsp) # 4-byte Spill je .LBB0_2 llvm-svn: 137303
* Stay within 80 columns.Devang Patel2011-08-102-22/+34
| | | | llvm-svn: 137283
* Distinguish between two copies of one inlined variable. Take 2.Devang Patel2011-08-101-3/+4
| | | | llvm-svn: 137253
* While extending definition range of a debug variable, consult lexical scopes ↵Devang Patel2011-08-101-10/+22
| | | | | | also. There is no point extending debug variable out side its lexical block. This provides 6x compile time speedup in some cases. llvm-svn: 137250
* Revert unintentional parts of previous check-in.Devang Patel2011-08-101-5/+2
| | | | llvm-svn: 137249
* Start using LexicalScopes utility. No intetional functionality change.Devang Patel2011-08-102-526/+113
| | | | llvm-svn: 137246
* Provide utility to extract and use lexical scoping information from machine ↵Devang Patel2011-08-102-0/+306
| | | | | | instructions. llvm-svn: 137237
* Trim an unneeded header.Jakob Stoklund Olesen2011-08-092-0/+2
| | | | llvm-svn: 137184
* Inflate register classes after coalescing.Jakob Stoklund Olesen2011-08-091-2/+35
| | | | | | | | | | | | | | | | | | | | | | | Coalescing can remove copy-like instructions with sub-register operands that constrained the register class. Examples are: x86: GR32_ABCD:sub_8bit_hi -> GR32 arm: DPR_VFP2:ssub0 -> DPR Recompute the register class of any virtual registers that are used by less instructions after coalescing. This affects code generation for the Cortex-A8 where we use NEON instructions for f32 operations, c.f. fp_convert.ll: vadd.f32 d16, d1, d0 vcvt.s32.f32 d0, d16 The register allocator is now free to use d16 for the temporary, and that comes first in the allocation order because it doesn't interfere with any s-registers. llvm-svn: 137133
* Move CalculateRegClass to MRI::recomputeRegClass.Jakob Stoklund Olesen2011-08-093-34/+36
| | | | | | | | This function doesn't have anything to do with spill weights, and MRI already has functions for manipulating the register class of a virtual register. llvm-svn: 137123
* Print variable's inline location in debug output.Devang Patel2011-08-091-2/+5
| | | | llvm-svn: 137096
* Rename member variables to follow coding standards.Jakob Stoklund Olesen2011-08-092-231/+232
| | | | | | No functional change. llvm-svn: 137094
* Move the RegisterCoalescer private to its implementation file.Jakob Stoklund Olesen2011-08-092-142/+123
| | | | | | RegisterCoalescer.h still has the CoalescerPair class interface. llvm-svn: 137088
* Refer to the RegisterCoalescer pass by ID.Jakob Stoklund Olesen2011-08-096-13/+8
| | | | | | | A public interface is no longer needed since RegisterCoalescer is not an analysis any more. llvm-svn: 137082
* Hoist hasLoadFromStackSlot and hasStoreToStackSlot.Jakob Stoklund Olesen2011-08-081-0/+36
| | | | | | | These the methods are target-independent since they simply scan the memory operands. They can live in TargetInstrInfoImpl. llvm-svn: 137063
* Simplify by creating parent first.Devang Patel2011-08-081-19/+14
| | | | llvm-svn: 137056
* Fix typo. Thanks, Andy!Jakob Stoklund Olesen2011-08-061-1/+1
| | | | llvm-svn: 137023
* Reject RS_Spill ranges from local splitting as well.Jakob Stoklund Olesen2011-08-051-4/+4
| | | | | | | All new local ranges are marked as RS_New now, so there is no need to attempt splitting of RS_Spill ranges any more. llvm-svn: 137002
* Only mark remainder intervals as RS_Spill after per-block splitting.Jakob Stoklund Olesen2011-08-051-2/+12
| | | | | | | | | | The local ranges created get to stay in the RS_New stage, just like for local and region splitting. This gives tryLocalSplit a bit more freedom the first time it sees one of these new local ranges. llvm-svn: 137001
* Remember to update LiveDebugVariables after per-block splitting.Jakob Stoklund Olesen2011-08-051-1/+5
| | | | llvm-svn: 136996
* Extract per-block splitting into its own method.Jakob Stoklund Olesen2011-08-051-23/+36
| | | | | | No functional change. llvm-svn: 136994
* Delete getMultiUseBlocks and splitSingleBlocks.Jakob Stoklund Olesen2011-08-052-38/+0
| | | | | | | These functions are no longer used, and they are easily replaced with a loop calling shouldSplitSingleBlock and splitSingleBlock. llvm-svn: 136993
* Also use shouldSplitSingleBlock() in the fallback splitting mode.Jakob Stoklund Olesen2011-08-051-8/+18
| | | | | | | Drop the use of SplitAnalysis::getMultiUseBlocks, there is no need to go through a SmallPtrSet any more. llvm-svn: 136992
* Split around single instructions to enable register class inflation.Jakob Stoklund Olesen2011-08-053-1/+35
| | | | | | | | | | | | | Normally, we don't create a live range for a single instruction in a basic block, the spiller does that anyway. However, when splitting a live range that belongs to a proper register sub-class, inserting these extra COPY instructions completely remove the constraints from the remainder interval, and it may be allocated from the larger super-class. The spiller will mop up these small live ranges if we end up spilling anyway. It calls them snippets. llvm-svn: 136989
* Detect proper register sub-classes.Jakob Stoklund Olesen2011-08-052-2/+18
| | | | | | | | | | | | | | | | | Some instructions require restricted register classes, but most of the time that doesn't affect register allocation. For example, some instructions don't work with the stack pointer, but that is a reserved register anyway. Sometimes it matters, GR32_ABCD only has 4 allocatable registers. For such a proper sub-class, the register allocator should try to enable register class inflation since that makes more registers available for allocation. Make sure only legal super-classes are considered. For example, tGPR is not a proper sub-class in Thumb mode, but in ARM mode it is. llvm-svn: 136981
* Fix liveness computations in BranchFolding.Jakob Stoklund Olesen2011-08-051-13/+16
| | | | | | | | | | | | | | | | | | | | | | | The old code would look at kills and defs in one pass over the instruction operands, causing problems with this code: %R0<def>, %CPSR<def,dead> = tLSLri %R5<kill>, 2, pred:14, pred:%noreg %R0<def>, %CPSR<def,dead> = tADDrr %R4<kill>, %R0<kill>, pred:14, %pred:%noreg The last instruction kills and redefines %R0, so it is still live after the instruction. This caused a register scavenger crash when compiling 483.xalancbmk for armv6. I am not including a test case because it requires too much bad luck to expose this old bug. First you need to convince the register allocator to use %R0 twice on the tADDrr instruction, then you have to convince BranchFolding to do something that causes it to run the register scavenger on he bad block. <rdar://problem/9898200> llvm-svn: 136973
* Temporarily revert r135528 which distinguishes between two copies of oneChandler Carruth2011-08-051-6/+2
| | | | | | | | | | | | | | | | | | | inlined variable, based on the discussion in PR10542. This explodes the runtime of several passes down the pipeline due to a large number of "copies" remaining live across a large function. This only shows up with both debug and opt, but when it does it creates a many-minute compile when self-hosting LLVM+Clang. There are several other cases that show these types of regressions. All of this is tracked in PR10542, and progress is being made on fixing the issue. Once its addressed, the re-instated, but until then this restores the performance for self-hosting and other opt+debug builds. Devang, let me know if this causes any trouble, or impedes fixing it in any way, and thanks for working on this! llvm-svn: 136953
* Count the total amount of stack space used in compiled functions.Jakob Stoklund Olesen2011-08-041-1/+4
| | | | | | Patch by Ivan Krasin! llvm-svn: 136921
* Print DBG_VALUE variable's location info as a comment.Devang Patel2011-08-041-1/+13
| | | | llvm-svn: 136916
* Increment counter inside insertDebugValue().Devang Patel2011-08-041-2/+1
| | | | llvm-svn: 136915
* Add counter.Devang Patel2011-08-041-1/+4
| | | | llvm-svn: 136901
* Correctly handle multiple DBG_VALUE instructions at the same SlotIndex.Jakob Stoklund Olesen2011-08-031-0/+3
| | | | | | | | | | | | It is possible to have multiple DBG_VALUEs for the same variable: 32L TEST32rr %vreg0<kill>, %vreg0, %EFLAGS<imp-def>; GR32:%vreg0 DBG_VALUE 2, 0, !"i" DBG_VALUE %noreg, %0, !"i" When that happens, keep the last one instead of the first. llvm-svn: 136842
* Enable compact region splitting by default.Jakob Stoklund Olesen2011-08-031-1/+1
| | | | | | | | | | | This helps generate better code in functions with high register pressure. The previous version of compact region splitting caused regressions because the regions were a bit too large. A stronger negative bias applied in r136832 fixed this problem. llvm-svn: 136836
* Do not drop undef debug values. These are used as range termination marker ↵Devang Patel2011-08-031-1/+1
| | | | | | by live debug variable pass. llvm-svn: 136834
* Be more conservative when forming compact regions.Jakob Stoklund Olesen2011-08-033-3/+8
| | | | | | | | | | | | | | | Apply twice the negative bias on transparent blocks when computing the compact regions. This excludes loop backedges from the region when only one of the loop blocks uses the register. Previously, we would include the backedge in the region if the loop preheader and the loop latch both used the register, but the loop header didn't. When both the header and latch blocks use the register, we still keep it live on the backedge. llvm-svn: 136832
* Fix some warnings from Clang in release builds:Chandler Carruth2011-08-031-0/+2
| | | | | | | | | | | lib/CodeGen/RegAllocGreedy.cpp:1176:18: warning: unused variable 'B' [-Wunused-variable] if (unsigned B = Cand.getBundles(BundleCand, BestCand)) { ^ lib/CodeGen/RegAllocGreedy.cpp:1188:18: warning: unused variable 'B' [-Wunused-variable] if (unsigned B = Cand.getBundles(BundleCand, 0)) { ^ llvm-svn: 136831
* Fix typo in #include which revealed in the case-sensitive filesystem.Jakub Staszak2011-08-031-1/+1
| | | | llvm-svn: 136828
* Use MachineBranchProbabilityInfo in If-Conversion instead of its own heuristics.Jakub Staszak2011-08-031-29/+10
| | | | llvm-svn: 136826
* Add more constantness in BlockFrequencyInfo.Jakub Staszak2011-08-031-1/+2
| | | | llvm-svn: 136816
* New approach to r136737: insert the necessary fences for atomic ops in ↵Eli Friedman2011-08-032-8/+60
| | | | | | | | platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing. I think this completes the basic CodeGen for atomicrmw and cmpxchg. llvm-svn: 136813
* Some revisions to Devang's change r136759 for merged global debug info.Bob Wilson2011-08-031-23/+9
| | | | llvm-svn: 136802
* Use byte offset, instead of element number, to access merged global.Devang Patel2011-08-031-3/+21
| | | | llvm-svn: 136759
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