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* [DebugInfo] Insert DEBUG_VALUEs after each register redefinitionKarl-Johan Karlsson2017-10-051-18/+57
| | | | | | | | | | | | | | | | | | | | | | | | Summary: When reinserting debug values after register allocation, make sure to insert debug values after each redefinition of debug value register in the slot index range. The reason for this is that DwarfDebug will end the range of a debug variable when the physical reg is defined. For instructions with e.g. tied operands this result in prematurely ended debug range. This resolves pr34545 Patch by Karl-Johan Karlsson and Bjorn Pettersson Reviewers: rnk, aprantl Reviewed By: rnk Subscribers: bjope, llvm-commits Differential Revision: https://reviews.llvm.org/D38229 llvm-svn: 314974
* Minor refactoring regarding Cast::isNoopCast(), NFCMikael Holmen2017-10-051-2/+1
| | | | | | | | | | | | | | | | | | | | | Summary: FastISel::hasTrivialKill() was the only user of the "IntPtrTy" version of Cast::isNoopCast(). According to review comments in D37894 we could instead use the "DataLayout" version of the method, and thus get rid of the "IntPtrTy" versions of isNoopCast() completely. With the above done, the remaining isNoopCast() could then be simplified a bit more. Reviewers: arsenm Reviewed By: arsenm Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D38497 llvm-svn: 314969
* [MachineBlockPlacement] Make sure PreferredLoopExit is cleared everytime new ↵Xin Tong2017-10-041-0/+10
| | | | | | | | | | | | | | loop is processed Summary: Rotate on exit that actually exits the current loop. Reviewers: davidxl, danielcdh, iteratee, chandlerc Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38563 llvm-svn: 314937
* [SimplifyCFG] put the optional assumption cache pointer in the options ↵Sanjay Patel2017-10-041-1/+1
| | | | | | | | | | | | struct; NFCI This is a follow-up to https://reviews.llvm.org/D38138. I fixed the capitalization of some functions because we're changing those lines anyway and that helped verify that we weren't accidentally dropping any options by using default param values. llvm-svn: 314930
* Revert r314886 "[X86] Improvement in CodeGen instruction selection for LEAs ↵Hans Wennborg2017-10-041-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (re-applying post required revision changes.)" It broke the Chromium / SQLite build; see PR34830. > Summary: > 1/ Operand folding during complex pattern matching for LEAs has been > extended, such that it promotes Scale to accommodate similar operand > appearing in the DAG. > e.g. > T1 = A + B > T2 = T1 + 10 > T3 = T2 + A > For above DAG rooted at T3, X86AddressMode will no look like > Base = B , Index = A , Scale = 2 , Disp = 10 > > 2/ During OptimizeLEAPass down the pipeline factorization is now performed over LEAs > so that if there is an opportunity then complex LEAs (having 3 operands) > could be factored out. > e.g. > leal 1(%rax,%rcx,1), %rdx > leal 1(%rax,%rcx,2), %rcx > will be factored as following > leal 1(%rax,%rcx,1), %rdx > leal (%rdx,%rcx) , %edx > > 3/ Aggressive operand folding for AM based selection for LEAs is sensitive to loops, > thus avoiding creation of any complex LEAs within a loop. > > Reviewers: lsaba, RKSimon, craig.topper, qcolombet, jmolloy > > Reviewed By: lsaba > > Subscribers: jmolloy, spatel, igorb, llvm-commits > > Differential Revision: https://reviews.llvm.org/D35014 llvm-svn: 314919
* [OptRemark] Move YAML writing to IRAdam Nemet2017-10-041-6/+0
| | | | | | | | | | | | Before the patch this was in Analysis. Moving it to IR and making it implicit part of LLVMContext::diagnose allows the full opt-remark facility to be used outside passes e.g. the pass manager. Jessica is planning to use this to report function size after each pass. The same could be used for time reports. Tested with BUILD_SHARED_LIBS=On. llvm-svn: 314909
* Also update MachineORE after r314874.Adam Nemet2017-10-041-4/+2
| | | | llvm-svn: 314908
* [X86] Improvement in CodeGen instruction selection for LEAs (re-applying ↵Jatin Bhateja2017-10-041-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | post required revision changes.) Summary: 1/ Operand folding during complex pattern matching for LEAs has been extended, such that it promotes Scale to accommodate similar operand appearing in the DAG. e.g. T1 = A + B T2 = T1 + 10 T3 = T2 + A For above DAG rooted at T3, X86AddressMode will no look like Base = B , Index = A , Scale = 2 , Disp = 10 2/ During OptimizeLEAPass down the pipeline factorization is now performed over LEAs so that if there is an opportunity then complex LEAs (having 3 operands) could be factored out. e.g. leal 1(%rax,%rcx,1), %rdx leal 1(%rax,%rcx,2), %rcx will be factored as following leal 1(%rax,%rcx,1), %rdx leal (%rdx,%rcx) , %edx 3/ Aggressive operand folding for AM based selection for LEAs is sensitive to loops, thus avoiding creation of any complex LEAs within a loop. Reviewers: lsaba, RKSimon, craig.topper, qcolombet, jmolloy Reviewed By: lsaba Subscribers: jmolloy, spatel, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D35014 llvm-svn: 314886
* Recommit [UnreachableBlockElim] Use COPY if PHI input is undefMikael Holmen2017-10-041-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This time invoking llc with "-march=x86-64" in the testcase, so we don't assume the default target is x86. Summary: If we have %vreg0<def> = PHI %vreg2<undef>, <BB#0>, %vreg3, <BB#2>; GR32:%vreg0,%vreg2,%vreg3 %vreg3<def,tied1> = ADD32ri8 %vreg0<kill,tied0>, 1, %EFLAGS<imp-def>; GR32:%vreg3,%vreg0 then we can't just change %vreg0 into %vreg3, since %vreg2 is actually undef. We would have to also copy the undef flag to be able to change the register. Instead we deal with this case like other cases where we can't just replace the register: we insert a COPY. The code creating the COPY already copied all flags from the PHI input, so the undef flag will be transferred as it should. Reviewers: kparzysz Reviewed By: kparzysz Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38235 llvm-svn: 314882
* Revert r314879 "[UnreachableBlockElim] Use COPY if PHI input is undef"Mikael Holmen2017-10-041-3/+2
| | | | | | Build-bots broke on the new testcase. I'll investigate and fix. llvm-svn: 314880
* [UnreachableBlockElim] Use COPY if PHI input is undefMikael Holmen2017-10-041-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: If we have %vreg0<def> = PHI %vreg2<undef>, <BB#0>, %vreg3, <BB#2>; GR32:%vreg0,%vreg2,%vreg3 %vreg3<def,tied1> = ADD32ri8 %vreg0<kill,tied0>, 1, %EFLAGS<imp-def>; GR32:%vreg3,%vreg0 then we can't just change %vreg0 into %vreg3, since %vreg2 is actually undef. We would have to also copy the undef flag to be able to change the register. Instead we deal with this case like other cases where we can't just replace the register: we insert a COPY. The code creating the COPY already copied all flags from the PHI input, so the undef flag will be transferred as it should. Reviewers: kparzysz Reviewed By: kparzysz Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38235 llvm-svn: 314879
* [MachineOutliner] Fix off-by-one in cost modelJessica Paquette2017-10-031-35/+36
| | | | | | | | | | This commit does two things. Firstly, it cleans up some of the benefit calculation wrt outlined functions and candidates. Secondly, it fixes an off-by-one bug in the cost model which was caused by the benefit value of an OutlinedFunction and Candidate differing by 1. It updates the remarks test to reflect this change. llvm-svn: 314836
* Implement David Blaikie's suggestion for comparison operatorsReid Kleckner2017-10-031-3/+8
| | | | llvm-svn: 314822
* [DebugInfo] Correctly coalesce DBG_VALUEs that mix direct and indirect valuesReid Kleckner2017-10-031-83/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This should fix a regression introduced by r313786, which switched from MachineInstr::isIndirectDebugValue() to checking if operand 1 is an immediate. I didn't have a test case for it until now. A single UserValue, which approximates a user variable, may have many DBG_VALUE instructions that disagree about whether the variable is in memory or in a virtual register. This will become much more common once we have llvm.dbg.addr, but you can construct such a test case manually today with llvm.dbg.value. Before this change, we would get two UserValues: one for direct and one for indirect DBG_VALUE instructions describing the same variable. If we build separate interval maps for direct and indirect locations, we will end up accidentally coalescing identical DBG_VALUE intervals that need to remain separate because they are broken up by intervals of the opposite direct-ness. Reviewers: aprantl Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D37932 llvm-svn: 314819
* Revert "Re-enable "[MachineCopyPropagation] Extend pass to do COPY source ↵Geoff Berry2017-10-033-636/+23
| | | | | | | | | | forwarding"" This reverts commit r314729. Another bug has been encountered in an out-of-tree target reported by Quentin. llvm-svn: 314814
* [CGP] Make optimizeMemoryInst capable of handling multiple AddrModesJohn Brawn2017-10-031-20/+154
| | | | | | | | | | | | | Currently optimizeMemoryInst requires that all of the AddrModes it sees are identical. This patch makes it capable of tracking multiple AddrModes, so long as they differ in at most one field. This patch does nothing by itself, but later patches will make use of it to insert or reuse phi or select instructions for the differing fields. Differential Revision: https://reviews.llvm.org/D38278 llvm-svn: 314795
* [CGP] In optimizeMemoryInst handle select similarly to phiJohn Brawn2017-10-031-7/+16
| | | | | | | | | | This lets us optimize away selects that perform the same address computation in two different ways and is also the first step towards being able to handle selects between two different, but compatible, address computations. Differential Revision: https://reviews.llvm.org/D38242 llvm-svn: 314794
* [WebAssembly] MC: Support for init_array and fini_arraySam Clegg2017-10-031-3/+5
| | | | | | Differential Revision: https://reviews.llvm.org/D37757 llvm-svn: 314783
* [DebugInfo] Handle endianness when moving debug info for split integer ↵Bjorn Pettersson2017-10-031-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | values (reapplied) Summary: Take the target's endianness into account when splitting the debug information in DAGTypeLegalizer::SetExpandedInteger. This patch fixes so that, for big-endian targets, the fragment expression corresponding to the high part of a split integer value is placed at offset 0, in order to correctly represent the memory address order. I have attached a PPC32 reproducer where the resulting DWARF pieces for a 64-bit integer were incorrectly reversed. Original patch was reverted due to using -stop-after=isel in the test case (but that is only working when AMDGPU target is included in the llc build). The test case has now been updated to use -stop-before=expand-isel-pseudos instead. Patch by: dstenb Reviewers: JDevlieghere, aprantl, dblaikie Reviewed By: JDevlieghere, aprantl, dblaikie Subscribers: nemanjai Differential Revision: https://reviews.llvm.org/D38172 llvm-svn: 314781
* [MiSched] - Simplify ProcResEntry accessJaved Absar2017-10-031-6/+8
| | | | | | | Reviewed by: @MatzeB Differential Revision: https://reviews.llvm.org/D38447 llvm-svn: 314775
* ISel type legalization: add debug messages. NFCI.Sjoerd Meijer2017-10-031-168/+196
| | | | | | | | | | This adds some more debug messages to the type legalizer and functions like PromoteNode, ExpandNode, ExpandLibCall in an attempt to make the debug messages a little bit more informative and useful. Differential Revision: https://reviews.llvm.org/D38450 llvm-svn: 314773
* [Legalizer] Add support for G_OR NarrowScalar.Quentin Colombet2017-10-032-0/+45
| | | | | | | | | | | | | | Legalize bitwise OR: A = BinOp<Ty> B, C into: B1, ..., BN = G_UNMERGE_VALUES B C1, ..., CN = G_UNMERGE_VALUES C A1 = BinOp<Ty/N> B1, C2 ... AN = BinOp<Ty/N> BN, CN A = G_MERGE_VALUES A1, ..., AN llvm-svn: 314760
* [PowerPC] Revert r314666.Tim Shen2017-10-021-7/+2
| | | | | | | | | See https://reviews.llvm.org/D38172. I tried to XFAIL it, but sometimes XPASS triggers the bot. Simply revert it. llvm-svn: 314739
* Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"Geoff Berry2017-10-023-23/+636
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issues addressed since original review: - Avoid bug in regalloc greedy/machine verifier when forwarding to use in an instruction that re-defines the same virtual register. - Fixed bug when forwarding to use in EarlyClobber instruction slot. - Fixed incorrect forwarding to register definitions that showed up in explicit_uses() iterator (e.g. in INLINEASM). - Moved removal of dead instructions found by LiveIntervals::shrinkToUses() outside of loop iterating over instructions to avoid instructions being deleted while pointed to by iterator. - Fixed ARMLoadStoreOptimizer bug exposed by this change in r311907. - The pass no longer forwards COPYs to physical register uses, since doing so can break code that implicitly relies on the physical register number of the use. - The pass no longer forwards COPYs to undef uses, since doing so can break the machine verifier by creating LiveRanges that don't end on a use (since the undef operand is not considered a use). [MachineCopyPropagation] Extend pass to do COPY source forwarding This change extends MachineCopyPropagation to do COPY source forwarding. This change also extends the MachineCopyPropagation pass to be able to be run during register allocation, after physical registers have been assigned, but before the virtual registers have been re-written, which allows it to remove virtual register COPY LiveIntervals that become dead through the forwarding of all of their uses. llvm-svn: 314729
* Remove trailing whitespace to trigger re-cmakingMichael Liao2017-10-021-1/+1
| | | | llvm-svn: 314728
* Eliminate ftrunc if source is know to be roundedStanislav Mekhanoshin2017-10-021-0/+13
| | | | | | Differential Revision: https://reviews.llvm.org/D38421 llvm-svn: 314688
* use range-for-loops; NFCISanjay Patel2017-10-021-9/+8
| | | | llvm-svn: 314676
* remove duplicate comments, reposition related functions; NFCSanjay Patel2017-10-021-56/+49
| | | | llvm-svn: 314669
* [Debug info] Handle endianness when moving debug info for split integer valuesBjorn Pettersson2017-10-021-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Take the target's endianness into account when splitting the debug information in DAGTypeLegalizer::SetExpandedInteger. This patch fixes so that, for big-endian targets, the fragment expression corresponding to the high part of a split integer value is placed at offset 0, in order to correctly represent the memory address order. I have attached a PPC32 reproducer where the resulting DWARF pieces for a 64-bit integer were incorrectly reversed. Patch by: dstenb Reviewers: JDevlieghere, aprantl, dblaikie Reviewed By: JDevlieghere, aprantl, dblaikie Subscribers: nemanjai Differential Revision: https://reviews.llvm.org/D38172 llvm-svn: 314666
* CodeGen: Fix pointer info in expandUnalignedLoad/StoreYaxun Liu2017-09-291-12/+21
| | | | | | | | | | | | Currently expandUnalignedLoad/Store uses place holder pointer info for temporary memory operand in stack, which does not have correct address space. This causes unaligned private double16 load/store to be lowered to flat_load instead of buffer_load for amdgcn target. This fixes failures of OpenCL conformance test basic/vload_private/vstore_private on target amdgcn---amdgizcl. Differential Revision: https://reviews.llvm.org/D35361 llvm-svn: 314566
* [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-09-2910-137/+204
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 314559
* [SystemZ] implement shouldCoalesce()Jonas Paulsson2017-09-291-1/+1
| | | | | | | | | | | | | | | | | | | Implement shouldCoalesce() to help regalloc avoid running out of GR128 registers. If a COPY involving a subreg of a GR128 is coalesced, the live range of the GR128 virtual register will be extended. If this happens where there are enough phys-reg clobbers present, regalloc will run out of registers (if there is not a single GR128 allocatable register available). This patch tries to allow coalescing only when it can prove that this will be safe by checking the (local) interval in question. Review: Ulrich Weigand, Quentin Colombet https://reviews.llvm.org/D37899 https://bugs.llvm.org/show_bug.cgi?id=34610 llvm-svn: 314516
* [MachineOutliner][NFC] Simplify logic in pruneCandidatesJessica Paquette2017-09-281-70/+61
| | | | | | | | | This commit yanks out the repeated sections of code in pruneCandidates into two lambdas: ShouldSkipCandidate and Prune. This simplifies the logic in pruneCandidates significantly, and reduces the chance of introducing bugs by folding all of the shared logic into one place. llvm-svn: 314475
* MIR: Serialize CaleeSavedInfo Restored flagMatthias Braun2017-09-282-7/+14
| | | | llvm-svn: 314449
* llvm-dwarfdump: implement --find for .apple_namesAdrian Prantl2017-09-281-8/+1
| | | | | | | | | | | | This patch implements the dwarfdump option --find=<name>. This option looks for a DIE in the accelerator tables and dumps it if found. This initial patch only adds support for .apple_names to keep the review small, adding the other sections and pubnames support should be trivial though. Differential Revision: https://reviews.llvm.org/D38282 llvm-svn: 314439
* [DebugInfo] Do not extend range for physreg in LiveDebugVariablesBjorn Pettersson2017-09-281-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: A DBG_VALUE that is referring to a physical register is valid up until the next def of the register, or the end of the basic block that it belongs to. LiveDebugVariables is computing live intervals (slot index ranges) for DBG_VALUE instructions, before regalloc, in order to be able to re-insert DBG_VALUE instructions again after regalloc. When the DBG_VALUE is mapping a variable to a physical register we do not need to compute the range. We should simply re-insert the DBG_VALUE at the start position. The problem that was found, resulting in this patch, was a situation when the DBG_VALUE was the last real use of the physical register. The computeIntervals/extendDef methods extended the range to cover the whole basic block, even though the physical register very well could be allocated to some virtual register inside the basic block. So the extended range could not be trusted. This patch is a preparation for https://reviews.llvm.org/D38229, where the goal is to insert DBG_VALUE after each new definition of a variable, even if the virtual registers that the variable was connected to has been coalesced into using the same physical register (e.g. due to two address instructions). For more info see https://bugs.llvm.org/show_bug.cgi?id=34545 Reviewers: aprantl, rnk, echristo Reviewed By: aprantl Subscribers: Ka-Ka, llvm-commits Differential Revision: https://reviews.llvm.org/D38140 llvm-svn: 314414
* Teach TargetInstrInfo::getInlineAsmLength to parse .space directives with ↵Alex Bradbury2017-09-281-10/+32
| | | | | | | | | | | | | | | | | | | | | | | | integer arguments It's currently quite difficult to test passes like branch relaxation, which requires branches with large displacement to be generated. The .space assembler directive makes it easy to create arbitrarily large basic blocks, but getInlineAsmLength is not able to parse it and so the size of the block is not correctly estimated. Other backends (AArch64, AMDGPU) introduce options just for testing that artificially restrict the ranges of branch instructions (e.g. aarch64-tbz-offset-bits). Although parsing a single form of the .space directive feels inelegant, it does allow a more direct testing approach. This patch adapts the .space parsing code from Mips16InstrInfo::getInlineAsmLength and removes it now the extra functionality is provided by the base implementation. I want to move this functionality to the generic getInlineAsmLength as 1) I need the same for RISC-V, and 2) I feel other backends will benefit from more direct testing of large branch displacements. Differential Revision: https://reviews.llvm.org/D37798 llvm-svn: 314393
* [RegAllocGreedy]: Allow recoloring of done register if it's non-tiedMikael Holmen2017-09-281-2/+14
| | | | | | | | | | | | | | | | | | | | | Summary: If we have a non-allocated register, we allow us to try recoloring of an already allocated and "Done" register, even if they are of the same register class, if the non-allocated register has at least one tied def and the allocated one has none. It should be easier to recolor the non-tied register than the tied one, so it might be an improvement even if they use the same regclasses. Reviewers: qcolombet Reviewed By: qcolombet Subscribers: llvm-commits, MatzeB Differential Revision: https://reviews.llvm.org/D38309 llvm-svn: 314388
* [DAGCombiner] Fix an off-by-one error in vector logicGeorge Burgess IV2017-09-281-2/+2
| | | | | | | | | Without this, we could end up trying to get the Nth (0-indexed) element from a subvector of size N. Differential Revision: https://reviews.llvm.org/D37880 llvm-svn: 314380
* [CodeGen] Fix some Clang-tidy modernize-use-default-member-init and Include ↵Eugene Zelenko2017-09-277-208/+284
| | | | | | What You Use warnings; other minor fixes (NFC). llvm-svn: 314363
* Cleanup some problems with LLVM_ENABLE_DUMP in release builds, andDon Hinton2017-09-272-1/+2
| | | | | | | | always set LLVM_ENABLE_DUMP=ON for +Asserts builds. Differential Revision: https://reviews.llvm.org/D38306 llvm-svn: 314346
* [MachineOutliner] AArch64: Avoid saving + restoring LR if possibleJessica Paquette2017-09-271-85/+86
| | | | | | | | | | | | | | | | This commit allows the outliner to avoid saving and restoring the link register on AArch64 when it is dead within an entire class of candidates. This introduces changes to the way the outliner interfaces with the target. For example, the target now interfaces with the outliner using a MachineOutlinerInfo struct rather than by using getOutliningCallOverhead and getOutliningFrameOverhead. This also improves several comments on the outliner's cost model. https://reviews.llvm.org/D36721 llvm-svn: 314341
* [CodeGen] Emit necessary .note sections for -fsplit-stackThan McIntosh2017-09-273-1/+16
| | | | | | | | | | | | | | | | | | | | | Summary: According to https://gcc.gnu.org/wiki/SplitStacks, the linker expects a zero-sized .note.GNU-split-stack section if split-stack is used (and also .note.GNU-no-split-stack section if it also contains non-split-stack functions), so it can handle the cases where a split-stack function calls non-split-stack function. This change adds the sections if needed. Fixes PR #34670. Reviewers: thanm, rnk, luqmana Reviewed By: rnk Subscribers: llvm-commits Patch by Cherry Zhang <cherryyz@google.com> Differential Revision: https://reviews.llvm.org/D38051 llvm-svn: 314335
* [SimplifyCFG] add a struct to house optional folds (PR34603)Sanjay Patel2017-09-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was intended to be no-functional-change, but it's not - there's a test diff. So I thought I should stop here and post it as-is to see if this looks like what was expected based on the discussion in PR34603: https://bugs.llvm.org/show_bug.cgi?id=34603 Notes: 1. The test improvement occurs because the existing 'LateSimplifyCFG' marker is not carried through the recursive calls to 'SimplifyCFG()->SimplifyCFGOpt().run()->SimplifyCFG()'. The parameter isn't passed down, so we pick up the default value from the function signature after the first level. I assumed that was a bug, so I've passed 'Options' down in all of the 'SimplifyCFG' calls. 2. I split 'LateSimplifyCFG' into 2 bits: ConvertSwitchToLookupTable and KeepCanonicalLoops. This would theoretically allow us to differentiate the transforms controlled by those params independently. 3. We could stash the optional AssumptionCache pointer and 'LoopHeaders' pointer in the struct too. I just stopped here to minimize the diffs. 4. Similarly, I stopped short of messing with the pass manager layer. I have another question that could wait for the follow-up: why is the new pass manager creating the pass with LateSimplifyCFG set to true no matter where in the pipeline it's creating SimplifyCFG passes? // Create an early function pass manager to cleanup the output of the // frontend. EarlyFPM.addPass(SimplifyCFGPass()); --> /// \brief Construct a pass with the default thresholds /// and switch optimizations. SimplifyCFGPass::SimplifyCFGPass() : BonusInstThreshold(UserBonusInstThreshold), LateSimplifyCFG(true) {} <-- switches get converted to lookup tables and loops may not be in canonical form If this is unintended, then it's possible that the current behavior of dropping the 'LateSimplifyCFG' setting via recursion was masking this bug. Differential Revision: https://reviews.llvm.org/D38138 llvm-svn: 314308
* [RegAllocGreedy] Fix spelling error, "inteference" -> "interference", NFCMikael Holmen2017-09-271-3/+3
| | | | llvm-svn: 314299
* [Misched]: Remove double call getMicroOpFactor.NFC.Javed Absar2017-09-271-1/+1
| | | | | | | Reviewed by: @MatzeB Differential Revision: https://reviews.llvm.org/D38176 llvm-svn: 314296
* [SelectionDAG] Make NewSDValueDbgMsg print target specific nodes correctly ↵Craig Topper2017-09-271-12/+12
| | | | | | by passing in the SelectionDAG. llvm-svn: 314271
* [SelectionDAG] Teach simplifyDemandedBits to handle shifts by constant splat ↵Craig Topper2017-09-251-62/+70
| | | | | | | | | | | | | | | | vectors This teach simplifyDemandedBits to handle constant splat vector shifts. This required changing some uses of getZExtValue to getLimitedValue since we can't rely on legalization using getShiftAmountTy for the shift amount. I believe there may have been a bug in the ((X << C1) >>u ShAmt) handling where we didn't check if the inner shift was too large. I've fixed that here. I had to add new patterns to ARM because the zext/sext the patterns were trying to look for got turned into an any_extend with this patch. Happy to split that out too, but not sure how to test without this change. Differential Revision: https://reviews.llvm.org/D37665 llvm-svn: 314139
* [DebugInfo] Sort the SDDbgValue list before assuming it is in IR orderReid Kleckner2017-09-251-9/+18
| | | | | | | | | | | | | | | | | | | | | | | Summary: This code iterates the 'Orders' vector in parallel with the DbgValue list, emitting all DBG_VALUEs that occurred between the last IR order insertion point and the next insertion point. This assumes the SDDbgValue list is sorted in IR order, which it usually is. However, it is not sorted when a node with a debug value is replaced with another one. When this happens, TransferDbgValues is called, and the new value is added to the end of the list. The problem can be solved by stably sorting the list by IR order. Reviewers: aprantl, Ka-Ka Reviewed By: aprantl Subscribers: MatzeB, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D38197 llvm-svn: 314114
* Use {} instead of make_pair and an iterator for the insertion point, NFCReid Kleckner2017-09-251-5/+6
| | | | llvm-svn: 314113
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