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* CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFCDuncan P. N. Exon Smith2016-02-2718-165/+163
| | | | | | | | | | | | | | Take MachineInstr by reference instead of by pointer in SlotIndexes and the SlotIndex wrappers in LiveIntervals. The MachineInstrs here are never null, so this cleans up the API a bit. It also incidentally removes a few implicit conversions from MachineInstrBundleIterator to MachineInstr* (see PR26753). At a couple of call sites it was convenient to convert to a range-based for loop over MachineBasicBlock::instr_begin/instr_end, so I added MachineBasicBlock::instrs. llvm-svn: 262115
* Minor code cleanup. NFC.Junmo Park2016-02-271-1/+1
| | | | llvm-svn: 262096
* Fix a bug in isVectorReductionOp() in SelectionDAGBuilder.cpp that may cause ↵Cong Hou2016-02-261-4/+4
| | | | | | assertion failure on AArch64. llvm-svn: 262091
* Fix warning in DwarfCFIException. NFCAmaury Sechet2016-02-261-1/+1
| | | | llvm-svn: 262061
* Extract the method to begin and end a fragment in AsmPrinterHandler in their ↵Amaury Sechet2016-02-264-12/+43
| | | | | | | | | | | | | | own method. NFC Summary: This is extracted from D17555 Reviewers: davidxl, reames, sanjoy, MatzeB, pete Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D17580 llvm-svn: 262058
* [GlobalISel] Fix a ranlib warning about empty TOC.Quentin Colombet2016-02-261-3/+6
| | | | | | Fixes PR26733 llvm-svn: 262057
* [WinEH] Fix funclet return block clobber mask placementReid Kleckner2016-02-261-2/+6
| | | | | | | | | | | | | | | | | | MBB slot index intervals are half open, not closed. getMBBEndIndex() returns the slot index of the start of the next block in layout order. Placing a register mask there is incorrect if the successor of the funclet return is not laid out after the return. Clang generates IR for catch bodies before generating the following normal code, so we never noticed this issue until the D frontend authors filed a bug about it. Instead, we can put the clobber mask on the last instruction of the funclet return block. We still aren't using a register mask operand on the CATCHRET instruction because it would cause PEI to spill all CSRs, including XMM regs, in the prologue. Fixes PR26679. llvm-svn: 262035
* MachineCopyPropagation: Catch copies of the form A<-B;A<-BMatthias Braun2016-02-261-54/+71
| | | | | | Differential Revision: http://reviews.llvm.org/D17475 llvm-svn: 261966
* MachineCopyPropagation: Keep scanning through instructions with regmasksMatthias Braun2016-02-261-55/+55
| | | | | | | | | | | | | | | | | | | | | | | This also simplifies the code by removing the overly conservative NoInterveningSideEffect() function. This function checked: - That the two copies belong to the same block: We only process one block at a time and clear our maps in between it is impossible to find a copy from a different block. - There is no terminator between the two copy instructions: This is not allowed anyway (the MachineVerifier would complain) - Does not have instructions with hasUnmodeledSideEffects() or isCall() set: Even for those instructuction we must have all clobbers/defs of registers explicit as an operand. If the register is explicitely clobbered we would never come to the point of checking for NoInterveningSideEffect() anyway. (I also checked this with a temporary build of the test-suite with all potentially failing conditions in NoInterveningSideEffect() turned into asserts) Differential Revision: http://reviews.llvm.org/D17474 llvm-svn: 261965
* Minor code cleanups. NFC.Junmo Park2016-02-261-3/+3
| | | | llvm-svn: 261955
* [WinEH] Don't remove unannotated inline-asm callsDavid Majnemer2016-02-261-2/+3
| | | | | | | | Inline-asm calls aren't annotated with funclet bundle operands because they don't throw and cannot be inlined through. We shouldn't require them to bear an funclet bundle operand. llvm-svn: 261942
* Introduce DominanceFrontierAnalysis to the new PassManager to compute ↵Hongbin Zheng2016-02-252-2/+2
| | | | | | | | DominanceFrontier. NFC Differential Revision: http://reviews.llvm.org/D17570 llvm-svn: 261903
* Introduce analysis pass to compute PostDominators in the new pass manager. NFCHongbin Zheng2016-02-251-1/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D17537 llvm-svn: 261902
* Revert "Introduce analysis pass to compute PostDominators in the new pass ↵Hongbin Zheng2016-02-251-1/+1
| | | | | | | | manager. NFC" This reverts commit a3e5cc6a51ab5ad88d1760c63284294a4e34c018. llvm-svn: 261891
* Revert "Introduce DominanceFrontierAnalysis to the new PassManager to ↵Hongbin Zheng2016-02-252-2/+2
| | | | | | | | compute DominanceFrontier. NFC" This reverts commit 109c38b2226a87b0be73fa7a0a8c1a81df20aeb2. llvm-svn: 261890
* Introduce DominanceFrontierAnalysis to the new PassManager to compute ↵Hongbin Zheng2016-02-252-2/+2
| | | | | | | | DominanceFrontier. NFC Differential Revision: http://reviews.llvm.org/D17570 llvm-svn: 261883
* Introduce analysis pass to compute PostDominators in the new pass manager. NFCHongbin Zheng2016-02-251-1/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D17537 llvm-svn: 261882
* [CodeGenPrepare] Remove load-based heuristicJunmo Park2016-02-251-11/+0
| | | | | | | | | | | | | | Summary: Both the hardware and LLVM have changed since 2012. Now, load-based heuristic don't show big differences any more on OoO cores. There is no notable regressons and improvements on spec2000/2006. (Cortex-A57, Core i5). Reviewers: spatel, zansari Differential Revision: http://reviews.llvm.org/D16836 llvm-svn: 261809
* Detecte vector reduction operations just before instruction selection.Cong Hou2016-02-241-0/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | (This is the second attemp to commit this patch, after fixing pr26652 & pr26653). This patch detects vector reductions before instruction selection. Vector reductions are vectorized reduction operations, and for such operations we have freedom to reorganize the elements of the result as long as the reduction of them stay unchanged. This will enable some reduction pattern recognition during instruction combine such as SAD/dot-product on X86. A flag is added to SDNodeFlags to mark those vector reduction nodes to be checked during instruction combine. To detect those vector reductions, we search def-use chains starting from the given instruction, and check if all uses fall into two categories: 1. Reduction with another vector. 2. Reduction on all elements. in which 2 is detected by recognizing the pattern that the loop vectorizer generates to reduce all elements in the vector outside of the loop, which includes several ShuffleVector and one ExtractElement instructions. Differential revision: http://reviews.llvm.org/D15250 llvm-svn: 261804
* MachineInstr: Respect register aliases in clearRegiserKills()Matthias Braun2016-02-241-1/+1
| | | | | | | | | | | | | | | This fixes bugs in copy elimination code in llvm. It slightly changes the semantics of clearRegisterKills(). This is appropriate because: - Users in lib/CodeGen/MachineCopyPropagation.cpp and lib/Target/AArch64RedundantCopyElimination.cpp and lib/Target/SystemZ/SystemZElimCompare.cpp are incorrect without it (see included testcase). - All other users in llvm are unaffected (they pass TRI==nullptr) - (Kill flags are optional anyway so removing too many shouldn't hurt.) Differential Revision: http://reviews.llvm.org/D17554 llvm-svn: 261763
* NFC. Move isDereferenceable to Loads.h/cppArtur Pilipenko2016-02-241-0/+1
| | | | | | | | | | This is a part of the refactoring to unify isSafeToLoadUnconditionally and isDereferenceablePointer functions. In subsequent change I'm going to eliminate isDerferenceableAndAlignedPointer from Loads API, leaving isSafeToLoadSpecualtively the only function to check is load instruction can be speculated. Reviewed By: hfinkel Differential Revision: http://reviews.llvm.org/D16180 llvm-svn: 261736
* Revert r261633 "Supporting all entities declared in lexical scope in LLVM ↵Hans Wennborg2016-02-236-199/+51
| | | | | | | | debug info." This and the corresponding Clang change caused PR26715. llvm-svn: 261671
* Supporting all entities declared in lexical scope in LLVM debug info.Amjad Aboud2016-02-236-51/+199
| | | | | | Differential Revision: http://reviews.llvm.org/D15976 llvm-svn: 261633
* [WinEH] Visit 'unwind to caller' catchswitches nested in catchswitchesDavid Majnemer2016-02-231-4/+8
| | | | | | | We had the right logic for the nested cleanuppad case but omitted it for catchswitches. llvm-svn: 261615
* Add prefix based function layout when profile is available.Dehao Chen2016-02-231-0/+16
| | | | | | | | | | | | Summary: If a function is hot, put it in text.hot section. Reviewers: davidxl Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D17532 llvm-svn: 261607
* CodeGen: TII: Take MachineInstr& in predicate API, NFCDuncan P. N. Exon Smith2016-02-238-57/+52
| | | | | | | | | | | | | Change TargetInstrInfo API to take `MachineInstr&` instead of `MachineInstr*` in the functions related to predicated instructions (I'll try to come back later and get some of the rest). All of these functions require non-null parameters already, so references are more clear. As a bonus, this happens to factor away a host of implicit iterator => pointer conversions. No functionality change intended. llvm-svn: 261605
* Revert "Add prefix based function layout when profile is available."Duncan P. N. Exon Smith2016-02-231-16/+0
| | | | | | | | This reverts commit r261582, since this bot has been broken for four hours: http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-incremental_check/19399/ llvm-svn: 261604
* Include ProfileData as CodeGen's required library.Dehao Chen2016-02-221-1/+1
| | | | | | | | | | | | Summary: Fixing buildbot failure introduced by http://reviews.llvm.org/D17460 Reviewers: davidxl, hans Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D17524 llvm-svn: 261588
* [X86] Create mergeable constant pool entries for AVXDavid Majnemer2016-02-222-2/+8
| | | | | | | We supported creating mergeable constant pool entries for smaller constants but not for 32-byte AVX constants. llvm-svn: 261584
* Add prefix based function layout when profile is available.Dehao Chen2016-02-221-0/+16
| | | | | | | | | | | | Summary: If a function is hot, put it in text.hot section. Reviewers: davidxl Subscribers: eraman, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17460 llvm-svn: 261582
* SelectionDAG: Use correct addrspace when lowering memcpyMatt Arsenault2016-02-221-9/+16
| | | | | | | | | | | This was causing assertions later from using the wrong pointer size with LDS operations. getOptimalMemOpType should also have address space arguments later. This avoids assertions in existing tests exposed by a future commit. llvm-svn: 261580
* ARM: sink atomic release barrier as far as possible into cmpxchg.Tim Northover2016-02-221-21/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | DMB instructions can be expensive, so it's best to avoid them if possible. In atomicrmw operations there will always be an attempted store so a release barrier is always needed, but in the cmpxchg case we can delay the DMB until we know we'll definitely try to perform a store (and so need release semantics). In the strong cmpxchg case this isn't quite free: we must duplicate the LDREX instructions to skip the barrier on subsequent iterations. The basic outline becomes: ldrex rOld, [rAddr] cmp rOld, rDesired bne Ldone dmb Lloop: strex rRes, rNew, [rAddr] cbz rRes Ldone ldrex rOld, [rAddr] cmp rOld, rDesired beq Lloop Ldone: So we'll skip this version for strong operations in "minsize" functions. llvm-svn: 261568
* Revert "CodeGen: MachineInstr::getIterator() => getInstrIterator(), NFC"Duncan P. N. Exon Smith2016-02-225-23/+25
| | | | | | | | | | This reverts commit r261504, since it's not obvious the new name is better: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20160222/334298.html I'll recommit if we get consensus that it's the right direction. llvm-svn: 261567
* Revert "[ifcnv] Add comment explaining why it's OK to duplicate convergent ↵Justin Lebar2016-02-221-5/+1
| | | | | | | | MIs in ifcnv." This reverts r261543. Accidental commit (not LGTM'ed). llvm-svn: 261547
* [ifcnv] Add comment explaining why it's OK to duplicate convergent MIs in ifcnv.Justin Lebar2016-02-221-1/+5
| | | | | | | | | | | | | | | Summary: Also add a comment briefly explaining what ifcnv is. No functional changes. Reviewers: resistor Subscribers: echristo, tra, llvm-commits Differential Revision: http://reviews.llvm.org/D17430 llvm-svn: 261543
* [ifcnv] Use unique_ptr in IfConversion. NFCJustin Lebar2016-02-221-26/+26
| | | | | | | | | | Reviewers: rnk Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D17466 llvm-svn: 261541
* Don't tail-duplicate blocks that contain convergent instructions.Justin Lebar2016-02-221-0/+5
| | | | | | | | | | | | | | | Summary: Convergent instrs shouldn't be made control-dependent on other values, but this is basically the whole point of tail duplication. So just bail if we see a convergent instruction. Reviewers: iteratee Subscribers: jholewinski, jhen, hfinkel, tra, jingyue, llvm-commits Differential Revision: http://reviews.llvm.org/D17320 llvm-svn: 261540
* Reapply "CodeGen: Use references in MachineTraceMetrics::Trace, NFC"Duncan P. N. Exon Smith2016-02-223-28/+27
| | | | | | | | | | | | | This reverts commit r261510, effectively reapplying r261509. The original commit missed a caller in AArch64ConditionalCompares. Original commit message: Pass non-null arguments by reference in MachineTraceMetrics::Trace, simplifying future work to remove implicit iterator => pointer conversions. llvm-svn: 261511
* Revert "CodeGen: Use references in MachineTraceMetrics::Trace, NFC"Duncan P. N. Exon Smith2016-02-223-27/+28
| | | | | | | This reverts commit r261509. I'm not sure how this compiled locally, but something was out of whack. llvm-svn: 261510
* CodeGen: Use references in MachineTraceMetrics::Trace, NFCDuncan P. N. Exon Smith2016-02-223-28/+27
| | | | | | | | Pass non-null arguments by reference in MachineTraceMetrics::Trace, simplifying future work to remove implicit iterator => pointer conversions. llvm-svn: 261509
* CodeGen: Explicitly convert from iterator to pointer, NFCDuncan P. N. Exon Smith2016-02-221-1/+1
| | | | llvm-svn: 261508
* CodeGen: MachineInstr::getIterator() => getInstrIterator(), NFCDuncan P. N. Exon Smith2016-02-215-25/+23
| | | | | | | | | | | | | | | | | | | | | | | Delete MachineInstr::getIterator(), since the term "iterator" is overloaded when talking about MachineInstr. - Downcast to ilist_node in iplist::getNextNode() and getPrevNode() so that ilist_node::getIterator() is still available. - Add it back as MachineInstr::getInstrIterator(). This matches the naming in MachineBasicBlock. - Add MachineInstr::getBundleIterator(). This is explicitly called "bundle" (not matching MachineBasicBlock) to disintinguish it clearly from ilist_node::getIterator(). - Update all calls. Some of these I switched to `auto` to remove boiler-plate, since the new name is clear about the type. There was one call I updated that looked fishy, but it wasn't clear what the right answer was. This was in X86FrameLowering::inlineStackProbe(), added in r252578 in lib/Target/X86/X86FrameLowering.cpp. I opted to leave the behaviour unchanged, but I'll reply to the original commit on the list in a moment. llvm-svn: 261504
* ADT: Remove == and != comparisons between ilist iterators and pointersDuncan P. N. Exon Smith2016-02-214-9/+11
| | | | | | | | | | | | | | I missed == and != when I removed implicit conversions between iterators and pointers in r252380 since they were defined outside ilist_iterator. Since they depend on getNodePtrUnchecked(), they indirectly rely on UB. This commit removes all uses of these operators. (I'll delete the operators themselves in a separate commit so that it can be easily reverted if necessary.) There should be NFC here. llvm-svn: 261498
* ADT: Stop using getNodePtrUnchecked on end() iteratorsDuncan P. N. Exon Smith2016-02-211-5/+3
| | | | | | | | | | | Stop using `getNodePtrUnchecked()` when building IR. Eventually a dereference will be required to get at the downcast node, since the iterator will only store an `ilist_node_base` of some sort. This should have no functionality change for now, but is a path towards removing some more UB from ilist. llvm-svn: 261495
* CodeGen: Avoid getNodePtrUnchecked() where we need a Value, NFCDuncan P. N. Exon Smith2016-02-211-4/+6
| | | | | | | | | | | | | | | `ilist_iterator<NodeTy>::getNodePtrUnchecked()` is documented as being for internal use only, but CodeGenPrepare was using it anyway. This code relies on pulling out the `Value*` pointer even after the lifetime of the iterator is over. But having this pointer available in ilist_iterator depends on UB in the first place. Instead, safely pull out the `Value*` when the iterator is alive and stop using the internal-only API. There should be no functionality change here. llvm-svn: 261493
* [X86] Use the correct alignment for COMDAT constant pool entriesDavid Majnemer2016-02-212-5/+8
| | | | | | | | | | | | | | | | | | | COFF doesn't have sections with mergeable contents. Instead, each constant pool entry ends up in a COMDAT section. The linker, when choosing between COMDAT sections, doesn't choose the max alignment of the two sections. You just get whatever alignment was on the section. If one constant needed a higher alignment in one object file from another one, then we will get into trouble if the linker chooses the lower alignment one. Instead, lets promote the alignment of the constant pool entry to make sure we don't use an under aligned constant with an instruction which assumed otherwise. This fixes PR26680. llvm-svn: 261462
* Don't scan for SSA register operands to update when not in SSA form.Dan Gohman2016-02-201-22/+24
| | | | | | | | | TailDuplicate can run on either on SSA code or non-SSA code, as indicated to it by MRI->isSSA() ("PreRegAlloc" here). TailDuplicate does extra work to preserve SSA invariants when it duplicates code. This patch makes it skip some of this extra work in the case where the code is not in SSA form. llvm-svn: 261450
* [DAGCombiner] Use getBitcast helper when possible. NFCI.Simon Pilgrim2016-02-201-7/+3
| | | | llvm-svn: 261437
* MachineCopyPropagation: Introduce Reg2MIMap typedef; NFCMatthias Braun2016-02-201-4/+5
| | | | llvm-svn: 261408
* MachineCopyPropagation: Move variables from function to passMatthias Braun2016-02-201-18/+22
| | | | | | | | This avoids unnecessarily passing them around when calling helper functions. It may also be slightly faster to call clear() on the datastructures instead of freshly initializing them for each block. llvm-svn: 261407
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