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* remove dead codeChris Lattner2005-12-222-7/+0
| | | | llvm-svn: 24965
* The 81st column doesn't like code in it.Chris Lattner2005-12-221-3/+4
| | | | llvm-svn: 24943
* Add an eol at the end to shut gcc sup.Reid Spencer2005-12-221-1/+1
| | | | llvm-svn: 24926
* * Fix a GlobalAddress lowering bug.Evan Cheng2005-12-211-1/+4
| | | | | | * Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook. llvm-svn: 24921
* Disengage DEBUG_LOC from non-PPC targets.Jim Laskey2005-12-212-13/+17
| | | | llvm-svn: 24919
* * Added support for X86 RET with an additional operand to specify number ofEvan Cheng2005-12-211-0/+10
| | | | | | | bytes to pop off stack. * Added support for X86 SETCC. llvm-svn: 24917
* Start of Dwarf framework.Jim Laskey2005-12-211-0/+15
| | | | llvm-svn: 24914
* make sure to relegalize all casesChris Lattner2005-12-211-1/+1
| | | | llvm-svn: 24911
* enable the gep isel optChris Lattner2005-12-211-6/+0
| | | | llvm-svn: 24910
* fix a bug I introduced that broke recursive expansion of nodes (e.g. ↵Chris Lattner2005-12-211-3/+6
| | | | | | scalarizing vectors) llvm-svn: 24905
* Lower ConstantAggregateZero into zerosChris Lattner2005-12-211-7/+20
| | | | llvm-svn: 24890
* Don't emit a null terminator, nor anything after it, to the ctor/dtor listChris Lattner2005-12-211-1/+4
| | | | llvm-svn: 24887
* Added a hook to print out names of target specific DAG nodes.Evan Cheng2005-12-201-5/+8
| | | | llvm-svn: 24877
* Fix a nasty latent bug in the legalizer that was triggered by my patchChris Lattner2005-12-201-22/+30
| | | | | | | | | | | last night, breaking crafty and twolf. Make sure that the newly found legal nodes are themselves not re-legalized until the next iteration. Also, since this functionality exists now, we can reduce number of legalizer iterations by depending on this behavior instead of having to misuse 'do another iteration' to get the same effect. llvm-svn: 24875
* X86 conditional branch support.Evan Cheng2005-12-191-0/+10
| | | | llvm-svn: 24870
* Print out opcode number if it's an unknown target node.Evan Cheng2005-12-191-1/+6
| | | | llvm-svn: 24869
* Fix a case where the DAG Combiner would accidentally CSE flag-producing nodes,Chris Lattner2005-12-191-1/+6
| | | | | | creating graphs that cannot be scheduled. llvm-svn: 24866
* Amend comment.Jim Laskey2005-12-191-1/+2
| | | | llvm-svn: 24861
* Create a strong dependency for loads following stores. This will leave aJim Laskey2005-12-191-2/+6
| | | | | | latency period between the two. llvm-svn: 24860
* Make sure to relegalize new nodesChris Lattner2005-12-181-11/+21
| | | | llvm-svn: 24843
* Keep VC++ happy.Jeff Cohen2005-12-181-0/+1
| | | | llvm-svn: 24835
* More corrections for flagged copyto/from regChris Lattner2005-12-181-8/+11
| | | | llvm-svn: 24828
* legalize copytoreg and copyfromreg nodes that have flag operands correctly.Chris Lattner2005-12-181-11/+34
| | | | llvm-svn: 24826
* Fix a bug Sabre was having where the DAG root was a group. The group dominatorJim Laskey2005-12-181-1/+6
| | | | | | needed to be added to the ordering list, not the first member of the group. llvm-svn: 24816
* Groups were not emitted if the dominator node and the node in the ordering listJim Laskey2005-12-181-10/+6
| | | | | | were not the same node. Ultimately the test was bogus. llvm-svn: 24815
* Simplify codeChris Lattner2005-12-181-7/+2
| | | | llvm-svn: 24806
* allow custom expansion of BR_CCChris Lattner2005-12-171-11/+25
| | | | llvm-svn: 24804
* X86 lowers SELECT to a cmp / test followed by a conditional move.Evan Cheng2005-12-171-0/+10
| | | | llvm-svn: 24754
* Added source file/line correspondence for dwarf (PowerPC only at this point.)Jim Laskey2005-12-164-5/+37
| | | | llvm-svn: 24748
* Don't create SEXTLOAD/ZEXTLOAD instructions that the target doesn't supportChris Lattner2005-12-151-2/+4
| | | | | | if after legalize. This fixes IA64 failures. llvm-svn: 24725
* When folding loads into ops, immediately replace uses of the op with theChris Lattner2005-12-141-6/+6
| | | | | | | | | load. This reduces number of worklist iterations and avoid missing optimizations depending on folding of things into sext_inreg nodes (which aren't supported by all targets). Tested by Regression/CodeGen/X86/extend.ll:test2 llvm-svn: 24712
* Fix the (zext (zextload)) case to trigger, similarly for sign extends.Chris Lattner2005-12-141-7/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow (zext (truncate)) to apply after legalize if the target supports AND (which all do). This compiles short %foo() { %tmp.0 = load ubyte* %X ; <ubyte> [#uses=1] %tmp.3 = cast ubyte %tmp.0 to short ; <short> [#uses=1] ret short %tmp.3 } to: _foo: movzbl _X, %eax ret instead of: _foo: movzbl _X, %eax movzbl %al, %eax ret thanks to Evan for pointing this out. llvm-svn: 24709
* Fix a miscompilation in crafty due to a recent patchChris Lattner2005-12-141-1/+1
| | | | llvm-svn: 24706
* Fold (zext (load x) to (zextload x).Evan Cheng2005-12-141-1/+18
| | | | llvm-svn: 24702
* Don't lump the filename and working dir togetherChris Lattner2005-12-131-15/+16
| | | | llvm-svn: 24697
* Add a couple more fields, move ctor init list to .cpp file, add supportChris Lattner2005-12-131-0/+70
| | | | | | for emitting the ctor/dtor list for common targets. llvm-svn: 24694
* Lowering constant pool entries on ppc exposed a bug in the recently addedNate Begeman2005-12-131-1/+1
| | | | | | | ConstantVec legalizing code, which would return constantpool nodes that were not of the target's pointer type. llvm-svn: 24691
* Accept and ignore prefetches for nowChris Lattner2005-12-121-0/+3
| | | | llvm-svn: 24678
* Fix CodeGen/Generic/2005-12-12-ExpandSextInreg.llChris Lattner2005-12-121-0/+10
| | | | llvm-svn: 24677
* Minor tweak to get isel optChris Lattner2005-12-111-1/+2
| | | | llvm-svn: 24663
* Add support for TargetConstantPool nodes to the dag isel emitter, and useNate Begeman2005-12-101-1/+3
| | | | | | | them in the PPC backend, to simplify some logic out of Select and SelectAddr. llvm-svn: 24657
* Added new getNode and getTargetNode variants for X86 stores.Evan Cheng2005-12-101-60/+73
| | | | llvm-svn: 24653
* Avoid emitting two tabs when switching to a named sectionChris Lattner2005-12-091-2/+2
| | | | llvm-svn: 24646
* Teach legalize how to promote sext_inreg to fix a problem Andrew pointedChris Lattner2005-12-091-0/+5
| | | | | | out to me. llvm-svn: 24644
* improve code insertion in two ways:Chris Lattner2005-12-081-20/+26
| | | | | | | | | | | | | 1. Only forward subst offsets into loads and stores, not into arbitrary things, where it will likely become a load. 2. If the source is a cast from pointer, forward subst the cast as well, allowing us to fold the cast away (improving cases when the cast is from an alloca or global). This hasn't been fully tested, but does appear to further reduce register pressure and improve code. Lets let the testers grind on it a bit. :) llvm-svn: 24640
* Fix a crash where ConstantVec nodes were being generated with the wrongNate Begeman2005-12-072-2/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | type when the target did not support them. Also teach Legalize how to expand ConstantVecs. This allows us to generate _test: lwz r2, 12(r3) lwz r4, 8(r3) lwz r5, 4(r3) lwz r6, 0(r3) addi r2, r2, 4 addi r4, r4, 3 addi r5, r5, 2 addi r6, r6, 1 stw r2, 12(r3) stw r4, 8(r3) stw r5, 4(r3) stw r6, 0(r3) blr For: void %test(%v4i *%P) { %T = load %v4i* %P %S = add %v4i %T, <int 1, int 2, int 3, int 4> store %v4i %S, %v4i * %P ret void } On PowerPC. llvm-svn: 24633
* Only transform (sext (truncate x)) -> (sextinreg x) if before legalize orChris Lattner2005-12-071-1/+3
| | | | | | if the target supports the resultant sextinreg llvm-svn: 24632
* Teach the dag combiner to turn a truncate/sign_extend pair into a sextinregChris Lattner2005-12-071-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when the types match up. This allows the X86 backend to compile: sbyte %toggle_value(sbyte* %tmp.1) { %tmp.2 = load sbyte* %tmp.1 ret sbyte %tmp.2 } to this: _toggle_value: mov %EAX, DWORD PTR [%ESP + 4] movsx %EAX, BYTE PTR [%EAX] ret instead of this: _toggle_value: mov %EAX, DWORD PTR [%ESP + 4] movsx %EAX, BYTE PTR [%EAX] movsx %EAX, %AL ret noticed in Shootout/objinst. -Chris llvm-svn: 24630
* Teach the SelectionDAG ISel how to turn ConstantPacked values intoNate Begeman2005-12-064-5/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | constant nodes with vector types. Also teach the asm printer how to print ConstantPacked constant pool entries. This allows us to generate altivec code such as the following, which adds a vector constantto a packed float. LCPI1_0: <4 x float> < float 0.0e+0, float 0.0e+0, float 0.0e+0, float 1.0e+0 > .space 4 .space 4 .space 4 .long 1065353216 ; float 1 .text .align 4 .globl _foo _foo: lis r2, ha16(LCPI1_0) la r2, lo16(LCPI1_0)(r2) li r4, 0 lvx v0, r4, r2 lvx v1, r4, r3 vaddfp v0, v1, v0 stvx v0, r4, r3 blr For the llvm code: void %foo(<4 x float> * %a) { entry: %tmp1 = load <4 x float> * %a; %tmp2 = add <4 x float> %tmp1, < float 0.0, float 0.0, float 0.0, float 1.0 > store <4 x float> %tmp2, <4 x float> *%a ret void } llvm-svn: 24616
* Fix the #1 code quality problem that I have seen on X86 (and it also affectsChris Lattner2005-12-051-6/+162
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PPC and other targets). In a particular, consider code like this: struct Vector3 { double x, y, z; }; struct Matrix3 { Vector3 a, b, c; }; double dot(Vector3 &a, Vector3 &b) { return a.x * b.x + a.y * b.y + a.z * b.z; } Vector3 mul(Vector3 &a, Matrix3 &b) { Vector3 r; r.x = dot( a, b.a ); r.y = dot( a, b.b ); r.z = dot( a, b.c ); return r; } void transform(Matrix3 &m, Vector3 *x, int n) { for (int i = 0; i < n; i++) x[i] = mul( x[i], m ); } we compile transform to a loop with all of the GEP instructions for indexing into 'm' pulled out of the loop (9 of them). Because isel occurs a bb at a time we are unable to fold the constant index into the loads in the loop, leading to PPC code that looks like this: LBB3_1: ; no_exit.preheader li r2, 0 addi r6, r3, 64 ;; 9 values live across the loop body! addi r7, r3, 56 addi r8, r3, 48 addi r9, r3, 40 addi r10, r3, 32 addi r11, r3, 24 addi r12, r3, 16 addi r30, r3, 8 LBB3_2: ; no_exit lfd f0, 0(r30) lfd f1, 8(r4) fmul f0, f1, f0 lfd f2, 0(r3) ;; no constant indices folded into the loads! lfd f3, 0(r4) lfd f4, 0(r10) lfd f5, 0(r6) lfd f6, 0(r7) lfd f7, 0(r8) lfd f8, 0(r9) lfd f9, 0(r11) lfd f10, 0(r12) lfd f11, 16(r4) fmadd f0, f3, f2, f0 fmul f2, f1, f4 fmadd f0, f11, f10, f0 fmadd f2, f3, f9, f2 fmul f1, f1, f6 stfd f0, 0(r4) fmadd f0, f11, f8, f2 fmadd f1, f3, f7, f1 stfd f0, 8(r4) fmadd f0, f11, f5, f1 addi r29, r4, 24 stfd f0, 16(r4) addi r2, r2, 1 cmpw cr0, r2, r5 or r4, r29, r29 bne cr0, LBB3_2 ; no_exit uh, yuck. With this patch, we now sink the constant offsets into the loop, producing this code: LBB3_1: ; no_exit.preheader li r2, 0 LBB3_2: ; no_exit lfd f0, 8(r3) lfd f1, 8(r4) fmul f0, f1, f0 lfd f2, 0(r3) lfd f3, 0(r4) lfd f4, 32(r3) ;; much nicer. lfd f5, 64(r3) lfd f6, 56(r3) lfd f7, 48(r3) lfd f8, 40(r3) lfd f9, 24(r3) lfd f10, 16(r3) lfd f11, 16(r4) fmadd f0, f3, f2, f0 fmul f2, f1, f4 fmadd f0, f11, f10, f0 fmadd f2, f3, f9, f2 fmul f1, f1, f6 stfd f0, 0(r4) fmadd f0, f11, f8, f2 fmadd f1, f3, f7, f1 stfd f0, 8(r4) fmadd f0, f11, f5, f1 addi r6, r4, 24 stfd f0, 16(r4) addi r2, r2, 1 cmpw cr0, r2, r5 or r4, r6, r6 bne cr0, LBB3_2 ; no_exit This is much nicer as it reduces register pressure in the loop a lot. On X86, this takes the function from having 9 spilled registers to 2. This should help some spec programs on X86 (gzip?) This is currently only enabled with -enable-gep-isel-opt to allow perf testing tonight. llvm-svn: 24606
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