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* Remove unused function argument, add a bit to the comment.Eric Christopher2012-11-202-5/+6
| | | | llvm-svn: 168387
* Formatting.Eric Christopher2012-11-201-10/+11
| | | | llvm-svn: 168384
* Whitespace.Eric Christopher2012-11-201-12/+8
| | | | llvm-svn: 168383
* Fix physical register liveness calculations:Tim Northover2012-11-202-8/+13
| | | | | | | + Take account of clobbers + Give outputs priority over inputs since they happen later. llvm-svn: 168360
* Remove a function argument and propagate const around accordingly.Eric Christopher2012-11-192-7/+11
| | | | llvm-svn: 168338
* Whitespace and 80-col.Eric Christopher2012-11-191-49/+49
| | | | llvm-svn: 168337
* Make AsmPrinter::EmitTTypeReference() more robust - putAnton Korobeynikov2012-11-193-19/+11
| | | | | | the zero GV check inside, so we won't forget it at the caller side. llvm-svn: 168328
* Factor out type info emission into separate routine.Anton Korobeynikov2012-11-193-2/+64
| | | | | | | It turned out that ARM wants different layout of type infos. This is yet another patch in attempt to fix PR7187 llvm-svn: 168325
* Move section label emission to module end. Nothing should beEric Christopher2012-11-191-3/+3
| | | | | | | depending on them being emitted before the text and/or data sections and testing didn't uncover any. llvm-svn: 168321
* Handle mixed normal and early-clobber defs on inline asm.Jakob Stoklund Olesen2012-11-191-2/+10
| | | | | | PR14376. llvm-svn: 168320
* Move else onto line with preceding closing brace.Craig Topper2012-11-191-2/+1
| | | | llvm-svn: 168294
* Broaden isSchedulingBoundary to check aliases of SP.Andrew Trick2012-11-171-1/+2
| | | | | | | | On PPC the stack pointer is X1, but ADJCALLSTACK writes R1. Fixes PR14315: Register regmask dependency problem with misched. llvm-svn: 168248
* Mark FP_EXTEND form v2f32 to v2f64 as "expand" for ARM NEON. Patch by Pete ↵Eli Friedman2012-11-171-0/+1
| | | | | | Couperus. llvm-svn: 168240
* Use array_pod_sort instead of std::sort.Andrew Trick2012-11-161-41/+36
| | | | llvm-svn: 168203
* Remove conditions from 'else if' that were guaranteed by preceding 'if'.Craig Topper2012-11-161-12/+12
| | | | llvm-svn: 168191
* Factor out the final FADD that's common to multiple code paths in the ↵Craig Topper2012-11-161-45/+30
| | | | | | visitLog* functions. llvm-svn: 168183
* Factor some common code to reduce compile size.Craig Topper2012-11-161-37/+20
| | | | llvm-svn: 168143
* Mark FP_ROUND for converting NEON v2f64 to v2f32 as expand. Add a missingEli Friedman2012-11-151-0/+1
| | | | | | | | case to vector legalization so this actually works. Patch by Pete Couperus. Fixes PR12540. llvm-svn: 168107
* Use std::stable_sort instead of std::sort when sorting stack slotsUlrich Weigand2012-11-151-1/+3
| | | | | | to guarantee deterministic code generation. llvm-svn: 168074
* [reg scavenger] Fix the isUsed/isAliasUsed functions so as to not report a falseChad Rosier2012-11-151-1/+1
| | | | | | | | | | | | | | | | positive. In this particular case, R6 was being spilled by the register scavenger when it was in fact dead. The isUsed function reported R6 as used because the R6_R7 alias was reserved (due to the fact that we've reserved R7 as the FP). The solution is to only check if the original register (i.e., R6) isReserved and not the aliases. The aliases are only checked to make sure they're available. The test case is derived from one of the nightly tester benchmarks and is rather intractable and difficult to reproduce, so I haven't included it. rdar://12592448 llvm-svn: 168054
* Fix indeterminism in MI scheduler DAG construction.Sergei Larin2012-11-151-15/+15
| | | | | | | Similarly to several recent fixes throughout the code replace std::map use with the MapVector. Add find() method to the MapVector. llvm-svn: 168051
* Add llvm.ceil, llvm.trunc, llvm.rint, llvm.nearbyint intrinsics.Craig Topper2012-11-151-0/+20
| | | | llvm-svn: 168025
* Fix an obvious merge bug in -join-globalcopies (disabled).Andrew Trick2012-11-151-1/+3
| | | | | | | | Jakub Staszak spotted this in review. I don't notice these things until I manually rerun benchmarks. But reducing unit tests is a very high priority. llvm-svn: 168021
* Use reserve() to avoid vector reallocation.Jakub Staszak2012-11-141-0/+1
| | | | llvm-svn: 167991
* canJoinPhys method doesn't modify CoalescerPair. Make it const.Jakub Staszak2012-11-141-2/+2
| | | | llvm-svn: 167972
* Remove dead code.Chad Rosier2012-11-141-13/+0
| | | | llvm-svn: 167970
* Fix really stupid ARM EHABI info generation bug: we should not emitAnton Korobeynikov2012-11-141-11/+14
| | | | | | | eh table and handler data if there are no landing pads in the function. Patch by Logan Chien with some cleanups from me. llvm-svn: 167945
* Add newlines to end of debug messages.Craig Topper2012-11-141-6/+6
| | | | llvm-svn: 167913
* Handle DAG CSE adding new uses during ReplaceAllUsesWith. Fixes PR14333.Rafael Espindola2012-11-141-1/+12
| | | | llvm-svn: 167912
* Use TARGET2 relocation for TType references on ARM.Anton Korobeynikov2012-11-143-45/+39
| | | | | | | | Do some cleanup of the code while here. Inspired by patch by Logan Chien! llvm-svn: 167904
* Revert "Use the 'count' attribute instead of the 'upper_bound' attribute."Eric Christopher2012-11-131-2/+1
| | | | | | | | temporarily as it is breaking the gdb bots. This reverts commit r167806/e7ff4c14b157746b3e0228d2dce9f70712d1c126. llvm-svn: 167886
* Revert -join-splitedges to a boolean cmd line option.Andrew Trick2012-11-131-3/+2
| | | | llvm-svn: 167880
* The MachineScheduler does not currently require JoinSplitEdges.Andrew Trick2012-11-131-4/+4
| | | | | | | This option will eventually either be enabled unconditionally or replaced by a more general live range splitting optimization. llvm-svn: 167879
* [MC][COFF] Emit weak symbols to the correct section. Patch by Dmitry Puzirev!Michael J. Spencer2012-11-131-2/+13
| | | | llvm-svn: 167877
* Do not consider a machine instruction that uses and defines the sameUlrich Weigand2012-11-131-16/+44
| | | | | | | | | | physical register as candidate for common subexpression elimination in MachineCSE. This fixes a bug on PowerPC in MultiSource/Applications/oggenc/oggenc caused by MachineCSE invalidly merging two separate DYNALLOC insns. llvm-svn: 167855
* Fix -join-splitedges: my previous "cleanup" broke it.Andrew Trick2012-11-131-1/+1
| | | | | | | Working on reducing unit tests. This won't be enabled unless a subtarget enables misched. llvm-svn: 167851
* Codegen support for arbitrary vector getelementptrs.Duncan Sands2012-11-131-3/+3
| | | | llvm-svn: 167830
* misched: Allow subtargets to enable misched and dependent options.Andrew Trick2012-11-134-14/+43
| | | | | | | | | | | | This allows me to begin enabling (or backing out) misched by default for one subtarget at a time. To run misched we typically want to: - Disable SelectionDAG scheduling (use the source order scheduler) - Enable more aggressive coalescing (until we decide to always run the coalescer this way) - Enable MachineScheduler pass itself. Disabling PostRA sched may follow for some subtargets. llvm-svn: 167826
* Added RegisterCoalescer support for joining global copies first.Andrew Trick2012-11-131-20/+80
| | | | | | | | | | | | This adds the -join-globalcopies option which can be enabled by default once misched is also enabled. Ideally, the register coalescer would be able to split local live ranges in a way that produces copies that can be easily resolved by the scheduler. Until then, this heuristic should be good enough to at least allow the scheduler to run after coalescing. llvm-svn: 167825
* misched: Don't consider artificial edges weak edges.Andrew Trick2012-11-132-9/+5
| | | | | | | For now be more conservative in case other out-of-tree schedulers rely on the old behavior of artificial edges. llvm-svn: 167808
* Use the 'count' attribute instead of the 'upper_bound' attribute.Bill Wendling2012-11-131-1/+2
| | | | | | | | | If we have a type 'int a[1]' and a type 'int b[0]', the generated DWARF is the same for both of them because we use the 'upper_bound' attribute. Instead use the 'count' attrbute, which gives the correct number of elements in the array. <rdar://problem/12566646> llvm-svn: 167806
* Cleanup the main RegisterCoalescer loop.Andrew Trick2012-11-131-23/+10
| | | | | | Block priorities still apply outside loops. llvm-svn: 167793
* Cleanup -join-splitedges. Make the loop more obvious.Andrew Trick2012-11-121-5/+2
| | | | llvm-svn: 167785
* Add an option to enable prototype "fission" capabilities and debug changes.Eric Christopher2012-11-122-0/+16
| | | | llvm-svn: 167765
* Added a temporary option to avoid critical edges splitting.Andrew Trick2012-11-121-16/+55
| | | | | | | | | This teaches the register coalescer to be less prone to split critical edges. I am currently benchmarking this with the new (post-coalescer) scheduler. I plan to enable this by default and remove the option as soon as misched is enabled. llvm-svn: 167758
* misched: rename interfaceto avoid gcc warningsAndrew Trick2012-11-121-2/+1
| | | | llvm-svn: 167753
* misched: Target-independent support for MacroFusion.Andrew Trick2012-11-121-5/+61
| | | | | | | | | Uses the infrastructure from r167742 to support clustering instructure that the target processor can "fuse". e.g. cmp+jmp. Next step: target hook implementations with test cases, and enable. llvm-svn: 167744
* misched: Target-independent support for load/store clustering.Andrew Trick2012-11-121-12/+176
| | | | | | | | | | This infrastructure is generally useful for any target that wants to strongly prefer two instructions to be adjacent after scheduling. A following checkin will add target-specific hooks with unit tests. Then this feature will be enabled by default with misched. llvm-svn: 167742
* misched: Infrastructure for weak DAG edges.Andrew Trick2012-11-126-45/+100
| | | | | | | | This adds support for weak DAG edges to the general scheduling infrastructure in preparation for MachineScheduler support for heuristics based on weak edges. llvm-svn: 167738
* Fix assertions in updateRegMaskSlots().Jakob Stoklund Olesen2012-11-091-4/+14
| | | | | | | | | The RegMaskSlots contains 'r' slots while NewIdx and OldIdx are 'B' slots. This broke the checks in the assertions. This fixes PR14302. llvm-svn: 167625
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