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* Add variables into a scope before constructing scope DIE otherwise variables ↵Devang Patel2010-06-301-2/+2
| | | | | | won't be included DIE tree. llvm-svn: 107228
* Begin implementation of an inline spiller.Jakob Stoklund Olesen2010-06-293-1/+147
| | | | | | | | | | | InlineSpiller inserts loads and spills immediately instead of deferring to VirtRegMap. This is possible now because SlotIndexes allows instructions to be inserted and renumbered. This is work in progress, and is mostly a copy of TrivialSpiller so far. It works very well for functions that don't require spilling. llvm-svn: 107227
* Revert r107205 and r107207.Bill Wendling2010-06-293-14/+11
| | | | llvm-svn: 107215
* Print InlinedAt location.Devang Patel2010-06-291-7/+21
| | | | llvm-svn: 107214
* Print InlinedAt location.Devang Patel2010-06-291-12/+23
| | | | llvm-svn: 107208
* Introducing the "linker_weak" linkage type. This will be used for Objective-CBill Wendling2010-06-293-11/+14
| | | | | | | | | | | | | | | | | | | metadata types which should be marked as "weak", but which the linker will remove upon final linkage. For example, the "objc_msgSend_fixup_alloc" symbol is defined like this: .globl l_objc_msgSend_fixup_alloc .weak_definition l_objc_msgSend_fixup_alloc .section __DATA, __objc_msgrefs, coalesced .align 3 l_objc_msgSend_fixup_alloc: .quad _objc_msgSend_fixup .quad L_OBJC_METH_VAR_NAME_1 This is different from the "linker_private" linkage type, because it can't have the metadata defined with ".weak_definition". llvm-svn: 107205
* Do not hardcode DW_AT_stmt_list value.Devang Patel2010-06-292-7/+17
| | | | | | Inspired by Artur Pietrek. llvm-svn: 107202
* Fix the handling of partial redefines in the fast register allocator.Jakob Stoklund Olesen2010-06-291-17/+39
| | | | | | | | | | | A partial redefine needs to be treated like a tied operand, and the register must be reloaded while processing use operands. This fixes a bug where partially redefined registers were processed as normal defs with a reload added. The reload could clobber another use operand if it was a kill that allowed register reuse. llvm-svn: 107193
* Fix a register scavenger crash when dealing with undefined subregs.Bob Wilson2010-06-291-0/+18
| | | | | | | The LowerSubregs pass needs to preserve implicit def operands attached to EXTRACT_SUBREG instructions when it replaces those instructions with copies. llvm-svn: 107189
* It seems clear that this should return Changed.Duncan Sands2010-06-291-1/+1
| | | | llvm-svn: 107141
* Add a VT argument to getMinimalPhysRegClass and replace the copy related usesRafael Espindola2010-06-294-7/+7
| | | | | | | | | of getPhysicalRegisterRegClass with it. If we want to make a copy (or estimate its cost), it is better to use the smallest class as more efficient operations might be possible. llvm-svn: 107140
* getMachineBasicBlockAddress returns a uintptr_t - don't truncateDuncan Sands2010-06-291-1/+1
| | | | | | | to unsigned only to extend back to a pointer sized value on the next line. llvm-svn: 107139
* use ArgOperand APIsGabor Greif2010-06-291-3/+3
| | | | llvm-svn: 107132
* Remove initialized but otherwise unused variables.Duncan Sands2010-06-292-3/+0
| | | | llvm-svn: 107127
* When processing loops for scheduling latencies (used for live outs on loopJim Grosbach2010-06-291-1/+4
| | | | | | | back-edges), make sure not to include dbg_value instructions in the count. Closing in on the end of rdar://7797940 llvm-svn: 107119
* Reapply my if-conversion cleanup from svn r106939 with fixes.Bob Wilson2010-06-291-34/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are 2 changes relative to the previous version of the patch: 1) For the "simple" if-conversion case, there's no need to worry about RemoveExtraEdges not handling an unanalyzable branch. Predicated terminators are ignored in this context, so RemoveExtraEdges does the right thing. This might break someday if we ever treat indirect branches (BRIND) as predicable, but for now, I just removed this part of the patch, because in the case where we do not add an unconditional branch, we rely on keeping the fall-through edge to CvtBBI (which is empty after this transformation). The change relative to the previous patch is: @@ -1036,10 +1036,6 @@ IterIfcvt = false; } - // RemoveExtraEdges won't work if the block has an unanalyzable branch, - // which is typically the case for IfConvertSimple, so explicitly remove - // CvtBBI as a successor. - BBI.BB->removeSuccessor(CvtBBI->BB); RemoveExtraEdges(BBI); // Update block info. BB can be iteratively if-converted. 2) My patch exposed a bug in the code for merging the tail of a "diamond", which had previously never been exercised. The code was simply checking that the tail had a single predecessor, but there was a case in MultiSource/Benchmarks/VersaBench/dbms where that single predecessor was neither edge of the diamond. I added the following change to check for that: @@ -1276,7 +1276,18 @@ // tail, add a unconditional branch to it. if (TailBB) { BBInfo TailBBI = BBAnalysis[TailBB->getNumber()]; - if (TailBB->pred_size() == 1 && !TailBBI.HasFallThrough) { + bool CanMergeTail = !TailBBI.HasFallThrough; + // There may still be a fall-through edge from BBI1 or BBI2 to TailBB; + // check if there are any other predecessors besides those. + unsigned NumPreds = TailBB->pred_size(); + if (NumPreds > 1) + CanMergeTail = false; + else if (NumPreds == 1 && CanMergeTail) { + MachineBasicBlock::pred_iterator PI = TailBB->pred_begin(); + if (*PI != BBI1->BB && *PI != BBI2->BB) + CanMergeTail = false; + } + if (CanMergeTail) { MergeBlocks(BBI, TailBBI); TailBBI.IsDone = true; } else { With these fixes, I was able to run all the SingleSource and MultiSource tests successfully. llvm-svn: 107110
* Unlike other targets, ARM now uses BUILD_VECTORs post-legalization so theyBob Wilson2010-06-281-1/+2
| | | | | | | can't be changed arbitrarily by the DAGCombiner without checking if it is running after legalization. llvm-svn: 107097
* Use DW_FORM_addr for DW_AT_entry_pc.Devang Patel2010-06-282-1/+3
| | | | llvm-svn: 107085
* In asm's, output operands with matching input constraintsDale Johannesen2010-06-281-2/+7
| | | | | | | | have to be registers, per gcc documentation. This affects the logic for determining what "g" should lower to. PR 7393. A couple of existing testcases are affected. llvm-svn: 107079
* Include inlined function in list of processed subprograms.Devang Patel2010-06-281-1/+1
| | | | llvm-svn: 107065
* new, no longer brain-dead, r106907Jim Grosbach2010-06-281-2/+9
| | | | llvm-svn: 107060
* After physreg coalescing, physical registers might not have live ranges whereJakob Stoklund Olesen2010-06-281-1/+2
| | | | | | | | | | you would expect. Don't assert on that case, just give up. This fixes PR7513. llvm-svn: 107046
* Add more special treatment for inline asm in RegAllocFast.Jakob Stoklund Olesen2010-06-281-21/+107
| | | | | | | | | | | | When an instruction has tied operands and physreg defines, we must take extra care that the tied operands conflict with neither physreg defs nor uses. The special treatment is given to inline asm and instructions with tied operands / early clobbers and physreg defines. This fixes PR7509. llvm-svn: 107043
* Preserve deleted function's local variables' debug info.Devang Patel2010-06-282-0/+39
| | | | | | Radar 8122864. llvm-svn: 107027
* simplify: we have solid argument iterator rangeGabor Greif2010-06-281-7/+4
| | | | llvm-svn: 107014
* Revert r106907, "make sure to handle dbg_value instructions in the middle of theDaniel Dunbar2010-06-281-10/+2
| | | | | | block, not...", it caused a bunch of nightly test regressions. llvm-svn: 107009
* Remove dead code.Devang Patel2010-06-282-3/+1
| | | | llvm-svn: 106990
* When splitting a VAARG, remember its alignment.Rafael Espindola2010-06-263-8/+28
| | | | | | This produces terrible but correct code. llvm-svn: 106952
* Revert my if-conversion cleanup since it caused a bunch of nightly testBob Wilson2010-06-261-37/+33
| | | | | | | | | | regressions. --- Reverse-merging r106939 into '.': U test/CodeGen/Thumb2/thumb2-ifcvt3.ll U lib/CodeGen/IfConversion.cpp llvm-svn: 106951
* VNInfos don't need to be destructed anymore.Benjamin Kramer2010-06-262-4/+4
| | | | llvm-svn: 106943
* Clean up some problems with extra CFG edges being introduced duringBob Wilson2010-06-261-33/+37
| | | | | | | | | | | | | | | if-conversion. The RemoveExtraEdges function doesn't work for blocks that end with unanalyzable branches, so in those cases, the "extra" edges must be explicitly removed. The CopyAndPredicateBlock and MergeBlocks methods can also avoid copying successor edges due to branches that have already been removed. The latter case is especially helpful when MergeBlocks is called for handling "diamond" if-conversions, where otherwise you can end up with some weird intermediate states in the CFG. Unfortunately I've been unable to find cases where this cleanup actually makes a significant difference in the code. There is one test where we manage to remove an empty block at the end of a function. Radar 6911268. llvm-svn: 106939
* make sure to handle dbg_value instructions in the middle of the block, notJim Grosbach2010-06-251-2/+10
| | | | | | just at the head, when doing diamond if-conversion. rdar://7797940 llvm-svn: 106907
* Don't track kills in VNInfo. Use interval ends instead.Jakob Stoklund Olesen2010-06-256-191/+79
| | | | | | | | | | | | The VNInfo.kills vector was almost unused except for all the code keeping it updated. The few places using it were easily rewritten to check for interval ends instead. The two new methods LiveInterval::killedAt and killedInRange are replacements. This brings us down to 3 independent data structures tracking kills. llvm-svn: 106905
* Change if-conversion block size limit checks to add some flexibility.Evan Cheng2010-06-252-14/+18
| | | | llvm-svn: 106901
* Collect debug info for optimized variables of inlined functions.Devang Patel2010-06-252-6/+30
| | | | llvm-svn: 106895
* 80 column and typo fixJim Grosbach2010-06-251-2/+2
| | | | llvm-svn: 106894
* The hasMemory argument is irrelevant to how the argumentDale Johannesen2010-06-252-7/+5
| | | | | | | | | for an "i" constraint should get lowered; PR 6309. While this argument was passed around a lot, this is the only place it was used, so it goes away from a lot of other places. llvm-svn: 106893
* - Reapply r106066 now that the bzip2 build regression has been fixed.Bill Wendling2010-06-251-50/+10
| | | | | | - 2010-06-25-CoalescerSubRegDefDead.ll is the testcase for r106878. llvm-svn: 106880
* We should remove the live range from the destination register only if *all* defsBill Wendling2010-06-251-2/+2
| | | | | | | | | are dead, not just the def of this register. I.e., a register could be dead, but it's subreg isn't. Testcase to follow with a subsequent patch. llvm-svn: 106878
* Cosmetic.Dale Johannesen2010-06-251-5/+2
| | | | llvm-svn: 106865
* Remove variables which are assigned to but for which the valueDuncan Sands2010-06-254-11/+1
| | | | | | is not used. Spotted by gcc-4.6. llvm-svn: 106854
* use ArgOperand accessorsGabor Greif2010-06-251-9/+14
| | | | | | | | | | and CallInst for getting hold of the intrinsic's arguments simplify along the way (at least for me this is much more legible now) Bill, Baldrick or Anton, please review\! llvm-svn: 106838
* use ArgOperand API (the simple part)Gabor Greif2010-06-251-2/+2
| | | | llvm-svn: 106837
* use ArgOperand APIGabor Greif2010-06-251-140/+140
| | | | llvm-svn: 106836
* use ArgOperand APIGabor Greif2010-06-251-1/+1
| | | | llvm-svn: 106835
* use ArgOperand API and CallSite to access arguments of CallInstGabor Greif2010-06-251-23/+26
| | | | llvm-svn: 106833
* use ArgOperand API and CallSite to access arguments of CallInstGabor Greif2010-06-252-9/+11
| | | | llvm-svn: 106829
* use ArgOperand APIGabor Greif2010-06-251-1/+1
| | | | llvm-svn: 106828
* prune an includeGabor Greif2010-06-251-1/+0
| | | | llvm-svn: 106827
* Fix a case where an earlyclobber operand of an asmDale Johannesen2010-06-251-0/+17
| | | | | | | | is reused as an input. PR 4118. Testcase is too big, as usual with bugs in this area, but there's one in the PR. llvm-svn: 106816
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