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* Remove unused variable.Benjamin Kramer2013-06-271-2/+0
| | | | llvm-svn: 185072
* Fixed a comment.Elena Demikhovsky2013-06-261-2/+2
| | | | llvm-svn: 184933
* Optimized integer vector multiplication operation by replacing it with ↵Elena Demikhovsky2013-06-261-20/+59
| | | | | | shift/xor/sub when it is possible. Fixed a bug in SDIV, where the const operand is not a splat constant vector. llvm-svn: 184931
* Remove unused code. No functionality change.Manman Ren2013-06-251-4/+0
| | | | llvm-svn: 184866
* BlockFrequency: Bump up the entry frequency a bit.Benjamin Kramer2013-06-251-5/+0
| | | | | | | This is a band-aid to fix the most severe regressions we're seeing from basing spill decisions on block frequencies, until we have a better solution. llvm-svn: 184835
* 80-column and tab character fixes.Eric Christopher2013-06-243-5/+8
| | | | llvm-svn: 184792
* Formatting.Eric Christopher2013-06-241-3/+2
| | | | llvm-svn: 184788
* Use const references instead of pointers to references that areEric Christopher2013-06-242-21/+23
| | | | | | never modified. No functional change. llvm-svn: 184781
* Fix tail merging to assign the (more) correct BasicBlock when splitting.Andrew Trick2013-06-242-5/+14
| | | | | | | | | | | This makes it possible to write unit tests that are less susceptible to minor code motion, particularly copy placement. block-placement.ll covers this case with -pre-RA-sched=source which will soon be default. One incorrectly named block is already fixed, but without this fix, enabling new coalescing and scheduling would cause more failures. llvm-svn: 184680
* DebugInfo: PR14404: Avoid truncating 64 bit values into 32 bits for ↵David Blaikie2013-06-231-2/+2
| | | | | | ULEB128/SLEB128 generation llvm-svn: 184669
* DebugInfo: Support (using GNU extensions) for template template parameters ↵David Blaikie2013-06-221-2/+11
| | | | | | and parameter packs llvm-svn: 184643
* The getRegForInlineAsmConstraint function should only accept MVT value types.Chad Rosier2013-06-221-1/+1
| | | | llvm-svn: 184642
* Prevent LiveRangeEdit from deleting bundled instructions.Andrew Trick2013-06-221-0/+4
| | | | | | | | | We have no targets on trunk that bundle before regalloc. However, we have been advertising regalloc as bundle safe for use with out-of-tree targets. We need to at least contain the parts of the code that are still unsafe. llvm-svn: 184620
* DebugInfo: Don't lose unreferenced non-trivial by-value parametersDavid Blaikie2013-06-211-6/+4
| | | | | | | | | | | | A FastISel optimization was causing us to emit no information for such parameters & when they go missing we end up emitting a different function type. By avoiding that shortcut we not only get types correct (very important) but also location information (handy) - even if it's only live at the start of a function & may be clobbered later. Reviewed/discussion by Evan Cheng & Dan Gohman. llvm-svn: 184604
* Fix PR16360Michael Liao2013-06-211-3/+5
| | | | | | | When (srl (anyextend x), c) is folded into (anyextend (srl x, c)), the high bits are not cleared. Add 'and' to clear off them. llvm-svn: 184575
* Update physreg live intervals during remat.Andrew Trick2013-06-211-0/+28
| | | | llvm-svn: 184574
* Added -precompute-phys-liveness for testing LiveIntervals updates.Andrew Trick2013-06-211-0/+14
| | | | llvm-svn: 184573
* Handle more cases in LiveRangeEdit::eliminateDeadDefs.Andrew Trick2013-06-211-0/+9
| | | | | | | | | | Live intervals for dead physregs may be created during coalescing. We need to update these in the event that their instruction goes away. crash.ll is the unit test that catches it when MI sched is enabled on X86. llvm-svn: 184572
* Refactor LiveRangeEdit::eliminateDeadDefs.Andrew Trick2013-06-211-95/+95
| | | | | | I want to add logic to handle more cases. llvm-svn: 184571
* whitespaceAndrew Trick2013-06-211-2/+2
| | | | llvm-svn: 184570
* Fix a -join-globalcopies bug; handle undef operands.Andrew Trick2013-06-211-0/+3
| | | | llvm-svn: 184569
* Modify the -join-globalcopies option (off by default).Andrew Trick2013-06-211-2/+2
| | | | | | | Always coalesce in forward order to propagate rematerialization. I'm fixing this option so I can enable it by default soon. llvm-svn: 184568
* Make rematerialization in the coalescer less sensitive to LRG order.Andrew Trick2013-06-211-4/+15
| | | | llvm-svn: 184567
* MI-Sched: cleanup DEBUG output.Andrew Trick2013-06-211-5/+6
| | | | llvm-svn: 184565
* MI-Sched: Adjust regpressure limits for reserved regs.Andrew Trick2013-06-213-6/+39
| | | | llvm-svn: 184564
* DebugInfo: don't use location lists when the location covers the whole ↵David Blaikie2013-06-203-9/+12
| | | | | | | | | | | | | function anyway Fix up three tests - one that was relying on abbreviation number, another relying on a location list in this case (& testing raw asm, changed that to use dwarfdump on the debug_info now that that's where the location is), and another which was added in r184368 - exposing a bug in that fix that is exposed when we emit the location inline rather than through a location list. Fix that bug while I'm here. llvm-svn: 184387
* This is now a duplicate.Bill Wendling2013-06-191-26/+0
| | | | llvm-svn: 184376
* Make the comparison operators non-member functions.Bill Wendling2013-06-191-2/+2
| | | | llvm-svn: 184373
* DebugInfo: PR14763/r183329 correct the location of indirect parametersDavid Blaikie2013-06-192-7/+10
| | | | | | | | | | | | | | | | We had been papering over a problem with location info for non-trivial types passed by value by emitting their type as references (this caused the debugger to interpret the location information correctly, but broke the type of the function). r183329 corrected the type information but lead to the debugger interpreting the pointer parameter as the value - the debug info describing the location needed an extra dereference. Use a new flag in DIVariable to add the extra indirection (either by promoting an existing DW_OP_reg (parameter passed in a register) to DW_OP_breg + 0 or by adding DW_OP_deref to an existing DW_OP_breg + n (parameter passed on the stack). llvm-svn: 184368
* Access the TargetLoweringInfo from the TargetMachine object instead of ↵Bill Wendling2013-06-194-236/+289
| | | | | | caching it. The TLI may change between functions. No functionality change. llvm-svn: 184360
* Access the TargetLoweringInfo from the TargetMachine object instead of ↵Bill Wendling2013-06-191-2/+2
| | | | | | caching it. The TLI may change between functions. No functionality change. llvm-svn: 184352
* Access the TargetLoweringInfo from the TargetMachine object instead of ↵Bill Wendling2013-06-196-39/+49
| | | | | | caching it. The TLI may change between functions. No functionality change. llvm-svn: 184349
* Don't cache the TLI object since we have access to it through TargetMachine ↵Bill Wendling2013-06-191-6/+8
| | | | | | already. llvm-svn: 184346
* During SelectionDAG building explicitly set a node to constant zero when theQuentin Colombet2013-06-181-0/+8
| | | | | | | | | | | | value is zero. This allows optmizations to kick in more easily. Fix some test cases so that they remain meaningful (i.e., not completely dead coded) when optimizations apply. <rdar://problem/14096009> superfluous multiply by high part of zero-extended value. llvm-svn: 184222
* Hopefully fix the MSVS build after r184105Timur Iskhodzhanov2013-06-181-0/+1
| | | | llvm-svn: 184178
* Use pointers to the MCAsmInfo and MCRegInfo.Bill Wendling2013-06-182-4/+3
| | | | | | | | | Someone may want to do something crazy, like replace these objects if they change or something. No functionality change intended. llvm-svn: 184175
* Simplify some of the code. No functionality change.Bill Wendling2013-06-181-7/+5
| | | | llvm-svn: 184172
* MI-Sched: handle ReadAdvance latencies as used by Swift.Andrew Trick2013-06-171-1/+4
| | | | llvm-svn: 184135
* Give RegMax higher priority.Andrew Trick2013-06-171-9/+9
| | | | llvm-svn: 184133
* Remove compareRPDelta.Andrew Trick2013-06-171-37/+0
| | | | | | A complex, expensive heuristic with little value in the current design. llvm-svn: 184132
* MI Sched: fix a typo in RegPressure heuristics.Andrew Trick2013-06-171-1/+1
| | | | llvm-svn: 184131
* MI-Sched: Remove another heuristic that is sensitive to queue order.Andrew Trick2013-06-171-6/+0
| | | | llvm-svn: 184130
* MI-Sched: Track multiple candidates with the same priority level.Andrew Trick2013-06-171-32/+25
| | | | | | | | This eliminates the MultiPressure scheduling "reason". It was sensitive to queue order. We don't like being sensitive to queue order. llvm-svn: 184129
* Directly access objects which may change during compilation.Bill Wendling2013-06-172-36/+68
| | | | llvm-svn: 184121
* Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo.Benjamin Kramer2013-06-1711-50/+60
| | | | | | | | | | | | | | | | | | The main advantages here are way better heuristics, taking into account not just loop depth but also __builtin_expect and other static heuristics and will eventually learn how to use profile info. Most of the work in this patch is pushing the MachineBlockFrequencyInfo analysis into the right places. This is good for a 5% speedup on zlib's deflate (x86_64), there were some very unfortunate spilling decisions in its hottest loop in longest_match(). Other benchmarks I tried were mostly neutral. This changes register allocation in subtle ways, update the tests for it. 2012-02-20-MachineCPBug.ll was deleted as it's very fragile and the instruction it looked for was gone already (but the FileCheck pattern picked up unrelated stuff). llvm-svn: 184105
* DebugInfo: remove target-specific Frame Index handling for DBG_VALUE ↵David Blaikie2013-06-161-8/+0
| | | | | | | | | | MachineInstrs Frame index handling is now target-agnostic, so delete the target hooks for creation & asm printing of target-specific addressing in DBG_VALUEs and any related functions. llvm-svn: 184067
* Debug Info: Simplify Frame Index handling in DBG_VALUE Machine InstructionsDavid Blaikie2013-06-1611-131/+112
| | | | | | | | | | | | | | | | | | | | Rather than using the full power of target-specific addressing modes in DBG_VALUEs with Frame Indicies, simply use Frame Index + Offset. This reduces the complexity of debug info handling down to two representations of values (reg+offset and frame index+offset) rather than three or four. Ideally we could ensure that frame indicies had been eliminated by the time we reached an assembly or dwarf generation, but I haven't spent the time to figure out where the FIs are leaking through into that & whether there's a good place to convert them. Some FI+offset=>reg+offset conversion is done (see PrologEpilogInserter, for example) which is necessary for some SelectionDAG assumptions about registers, I believe, but it might be possible to make this a more thorough conversion & ensure there are no remaining FIs no matter how instruction selection is performed. llvm-svn: 184066
* DebugInfo: print DBG_VALUE MachineInstrs with [] for deref and drop the ↵David Blaikie2013-06-151-3/+13
| | | | | | offset when it's zero llvm-svn: 184045
* Missing NDEBUGs.Andrew Trick2013-06-151-0/+6
| | | | llvm-svn: 184039
* MI-Sched: heuristics using the new latency and machine model.Andrew Trick2013-06-151-234/+330
| | | | llvm-svn: 184038
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