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* Use MachineBranchProbabilityInfo instead of MachineLoopInfo in IfConversion.Jakub Staszak2011-07-211-29/+10
| | | | llvm-svn: 135724
* Add missing getAnalysisUsage in MachineBlockFrequency.Jakub Staszak2011-07-211-0/+1
| | | | llvm-svn: 135714
* Refactor.Devang Patel2011-07-202-31/+42
| | | | llvm-svn: 135633
* There are two ways to map a variable to its lexical scope. Lexical scope ↵Devang Patel2011-07-201-2/+10
| | | | | | information is embedded in MDNode describing the variable. It is also available as a part of DebugLoc attached with DBG_VALUE instruction. DebugLoc attached with an instruction is less reliable in optimized code so use information embedded in the MDNode. llvm-svn: 135629
* While emitting constant value, look through derived type and use underlying ↵Devang Patel2011-07-201-14/+23
| | | | | | basic type to determine size and signness of the constant value. llvm-svn: 135627
* Goodbye TargetAsmInfo. This eliminate last bit of CodeGen and Target in llvm-mc.Evan Cheng2011-07-205-29/+7
| | | | | | | There is still a bit more refactoring left to do in Targets. But we are now very close to fixing all the layering issues in MC. llvm-svn: 135611
* PR10421: Fix a straightforward bug in the widening logic for CONCAT_VECTORS.Eli Friedman2011-07-201-5/+5
| | | | llvm-svn: 135595
* - Move CodeModel from a TargetMachine global option to MCCodeGenInfo.Evan Cheng2011-07-201-21/+2
| | | | | | | | - Introduce JITDefault code model. This tells targets to set different default code model for JIT. This eliminates the ugly hack in TargetMachine where code model is changed after construction. llvm-svn: 135580
* Add MCObjectFileInfo and sink the MCSections initialization code fromEvan Cheng2011-07-206-527/+13
| | | | | | | | TargetLoweringObjectFileImpl down to MCObjectFileInfo. TargetAsmInfo is done to one last method. It's *almost* gone! llvm-svn: 135569
* Fix an obvious typo that's preventing x86 (32-bit) from using .literal16.Evan Cheng2011-07-191-1/+1
| | | | llvm-svn: 135535
* Distinguish between two copies of one inlined variable.Devang Patel2011-07-191-2/+6
| | | | llvm-svn: 135528
* Convert TargetData::getIndexedOffset to use ArrayRef.Jay Foad2011-07-192-4/+2
| | | | llvm-svn: 135478
* Introduce MCCodeGenInfo, which keeps information that can affect codegenEvan Cheng2011-07-191-1/+3
| | | | | | | (including compilation, assembly). Move relocation model Reloc::Model from TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine. llvm-svn: 135468
* Revert r135423.Devang Patel2011-07-192-24/+0
| | | | llvm-svn: 135454
* Add a frame with the compact unwind encoding if it exists.Bill Wendling2011-07-191-0/+3
| | | | llvm-svn: 135450
* Rename CompactEncoding to CompactUnwindEncoding.Bill Wendling2011-07-191-2/+2
| | | | llvm-svn: 135448
* Move the compact encoding from the target-specific library to the code-genBill Wendling2011-07-181-3/+4
| | | | | | library. llvm-svn: 135443
* Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions forEvan Cheng2011-07-186-6/+3
| | | | | | better location welcome). llvm-svn: 135438
* Add APInt(numBits, ArrayRef<uint64_t> bigVal) constructor to prevent future ↵Jeffrey Yasskin2011-07-183-9/+9
| | | | | | | | | ambiguity errors like the one corrected by r135261. Migrate all LLVM callers of the old constructor to the new one. llvm-svn: 135431
* Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo downEvan Cheng2011-07-183-4/+8
| | | | | | | | | to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. llvm-svn: 135424
* During bottom up fast-isel, instructions emitted to materalize registers are ↵Devang Patel2011-07-182-0/+24
| | | | | | | | at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases. [take 2] llvm-svn: 135423
* Fix a crash when building 177.mesa for armv6.Jakob Stoklund Olesen2011-07-181-1/+1
| | | | | | | | | | | | When splitting a live range immediately before an LDR_POST instruction that redefines the address register, make sure to use the correct value number in leaveIntvBefore. We need the value number entering the instruction. <rdar://problem/9793765> llvm-svn: 135413
* Migrate LLVM and Clang to use the new makeArrayRef(...) functions where ↵Frits van Bommel2011-07-183-6/+5
| | | | | | | | previously explicit non-default constructors were used. Mostly mechanical with some manual reformatting. llvm-svn: 135390
* Fix PR10387.Jakob Stoklund Olesen2011-07-181-1/+1
| | | | | | | | | | | | | When trying to rematerialize a value before an instruction that has an early-clobber redefine of the virtual register, make sure to look up the correct value number. Early-clobber defs are moved one slot back, so getBaseIndex is needed to find the used value number. Bugpoint was unable to reduce the test case for this, see PR10388. llvm-svn: 135378
* land David Blaikie's patch to de-constify Type, with a few tweaks.Chris Lattner2011-07-1819-112/+112
| | | | llvm-svn: 135375
* Minor code cleanupsNadav Rotem2011-07-171-7/+6
| | | | llvm-svn: 135362
* Remove unused LoopRanges from RegAllocGreedy.Jakub Staszak2011-07-161-6/+0
| | | | llvm-svn: 135354
* Add MachineBlockFrequency analysis.Jakub Staszak2011-07-162-0/+60
| | | | llvm-svn: 135352
* Silence unused variable warningMatt Beaumont-Gay2011-07-161-0/+1
| | | | llvm-svn: 135339
* He said *before* the last split point.Jakob Stoklund Olesen2011-07-161-1/+1
| | | | | | | This should unbreak the build-self-4-mingw32 tester. I have a very complicated test case that I will try to clean up. llvm-svn: 135329
* LegalizeDAG doesn't need its own copy of this enum.Dan Gohman2011-07-151-7/+1
| | | | llvm-svn: 135320
* Delete LegalizeDAG's own version of isTypeLegal and getTypeActionDan Gohman2011-07-151-26/+16
| | | | | | and just use the ones from TargetLowering directly. llvm-svn: 135318
* Delete an unused variable and a redundant assert.Dan Gohman2011-07-151-9/+1
| | | | llvm-svn: 135311
* Extract parts of RAGreedy::splitAroundRegion as SplitKit methods.Jakob Stoklund Olesen2011-07-153-299/+308
| | | | | | | | | | | This gets rid of some of the gory splitting details in RAGreedy and makes them available to future SplitKit clients. Slightly generalize the functionality to support multi-way splitting. Specifically, SplitEditor::splitLiveThroughBlock() supports switching between different register intervals in a block. llvm-svn: 135307
* Modernize comments.Dan Gohman2011-07-151-7/+4
| | | | llvm-svn: 135305
* Use DebugLoc directly to map inlined functions' instructions to respective ↵Devang Patel2011-07-152-5/+9
| | | | | | lexical scope. llvm-svn: 135302
* Eliminate redundant map.Devang Patel2011-07-152-12/+3
| | | | llvm-svn: 135278
* Convert CallInst and InvokeInst APIs to use ArrayRef.Jay Foad2011-07-154-6/+4
| | | | llvm-svn: 135265
* Reverting r135232. It's causing infinite looping in DbgScope::openInsnRange.Evan Cheng2011-07-151-13/+5
| | | | llvm-svn: 135254
* Do not get confused by multiple empty lexical scopes inlined at one location. Devang Patel2011-07-151-5/+13
| | | | llvm-svn: 135232
* Rename createAsmInfo to createMCAsmInfo and move registration code to ↵Evan Cheng2011-07-141-1/+1
| | | | | | MCTargetDesc to prepare for next round of changes. llvm-svn: 135219
* Refactor.Devang Patel2011-07-142-19/+9
| | | | llvm-svn: 135212
* Eliminate redundant LLVMContext argument.Devang Patel2011-07-142-9/+11
| | | | | | Improve DbgScope->dump() output. llvm-svn: 135207
* Check register class matching instead of width of type matchingEric Christopher2011-07-142-6/+11
| | | | | | | | | when determining validity of matching constraint. Allow i1 types access to the GR8 reg class for x86. Fixes PR10352 and rdar://9777108 llvm-svn: 135180
* Change Intrinsic::getDeclaration and friends to take an ArrayRef.Benjamin Kramer2011-07-141-2/+1
| | | | llvm-svn: 135154
* [VECTOR-SELECT]Nadav Rotem2011-07-141-1/+1
| | | | | | | | | | | During type legalization we often use the SIGN_EXTEND_INREG SDNode. When this SDNode is legalized during the LegalizeVector phase, it is scalarized because non-simple types are automatically marked to be expanded. In this patch we add support for lowering SIGN_EXTEND_INREG manually. This fixes CodeGen/X86/vec_sext.ll when running with the '-promote-elements' flag. llvm-svn: 135144
* Add assertion for the chain value typeNadav Rotem2011-07-141-0/+10
| | | | llvm-svn: 135143
* Reapply r135121 with a fixed copy constructor.Jakob Stoklund Olesen2011-07-143-11/+70
| | | | | | | | | | | | | | | | | | | | | Original commit message: Count references to interference cache entries. Each InterferenceCache::Cursor instance references a cache entry. A non-zero reference count guarantees that the entry won't be reused for a new register. This makes it possible to have multiple live cursors examining interference for different physregs. The total number of live cursors into a cache must be kept below InterferenceCache::getMaxCursors(). Code generation should be unaffected by this change, and it doesn't seem to affect the cache replacement strategy either. llvm-svn: 135130
* Simplify.Devang Patel2011-07-141-13/+3
| | | | llvm-svn: 135127
* Don't emit a bit test if there is only one case the test can yield false. A ↵Benjamin Kramer2011-07-141-1/+9
| | | | | | simple SETNE is sufficient. llvm-svn: 135126
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