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* Add a parameter to CCState so that it can access the MachineFunction.Eric Christopher2011-06-083-14/+19
| | | | | | | | No functional change. Part of PR6965 llvm-svn: 132763
* Remove a temporary test case probe in CheckForLiveRegDef.Andrew Trick2011-06-081-1/+0
| | | | llvm-svn: 132751
* Fix count.Rafael Espindola2011-06-081-1/+1
| | | | llvm-svn: 132749
* Count how many phis we are creating.Rafael Espindola2011-06-081-0/+2
| | | | llvm-svn: 132748
* Fix an issue where the two-address conversion pass incorrectly rewrites untiedCameron Zwarich2011-06-071-9/+16
| | | | | | operands to an early clobber register. This fixes <rdar://problem/9566076>. llvm-svn: 132738
* Fix a silly error I introduce in r131951.Rafael Espindola2011-06-071-4/+1
| | | | | | Fixes PR10095. llvm-svn: 132735
* Fix a merge bug in preRAsched for handling physreg aliases.Andrew Trick2011-06-071-4/+6
| | | | | | | I've been sitting on this long enough trying to find a test case. I think the fix should go in now, but I'll keep working on the test case. llvm-svn: 132701
* Simplify local live range splitting's safeguard to fix PR10070.Jakob Stoklund Olesen2011-06-061-87/+57
| | | | | | | | | | | | | | | When local live range splitting creates a live range with the same number of instructions as the old range, mark it as RS_Local. When such a range is seen again, require that it be split in a way that reduces the number of instructions. That guarantees we are making progress while still being able to perform 3 -> 2+3 splits as required by PR10070. This also means that the PrevSlot map is no longer needed. This was also used to estimate new spill weights, but that is no longer necessary after slotIndexes::insertMachineInstrInMaps() got the extra Late insertion argument. llvm-svn: 132697
* Get allocation orders from RegisterClassInfo when possible.Jakob Stoklund Olesen2011-06-062-23/+52
| | | | | | | | | | | | Only target-dependent hints require callbacks. The RCI allocation order has CSR aliases last according to their order of appearance in the getCalleeSavedRegs list. This can depend on the calling convention. This way, AllocationOrder::next doesn't have to check for reserved registers, and CSRs are always allocated last, even with weird calling conventions. llvm-svn: 132690
* Add methods to support the integer-promotion of vector types. Methods toNadav Rotem2011-06-063-0/+192
| | | | | | legalize SDNodes such as BUILD_VECTOR, EXTRACT_VECTOR_ELT, etc. llvm-svn: 132689
* Avoid FGETSIGN of 80-bit types. Fixes PR10085.Stuart Hastings2011-06-061-6/+8
| | | | llvm-svn: 132681
* Don't try to be clever, just preserve the target's allocation order.Jakob Stoklund Olesen2011-06-061-11/+6
| | | | | | | | | | | | | | | The order of registers returned by getCalleeSavedRegs is used to lay out the fixed stack slots for CSRs. Some targets like their CSRs used from one end, and some targets want them used from the other end. When computing an allocation order, simply preserve the relative ordering of CSRs that the target specifies in its allocation order. Reordering CSRs would break some targets, ARM in particular. We still place volatiles before the CSRs, providing slightly better results with different calling conventions. llvm-svn: 132680
* PR10077: fix fast-isel of extractvalue of aggregate constants.Eli Friedman2011-06-061-1/+3
| | | | llvm-svn: 132676
* Use path API for path concatenation.Benjamin Kramer2011-06-051-5/+3
| | | | llvm-svn: 132668
* TypeLegalizer: Add support for passing of vector-promoted types in registers ↵Nadav Rotem2011-06-041-2/+40
| | | | | | (copyFromParts/copyToParts). llvm-svn: 132649
* TypeLegalizer: Fix a bug in the promotion of elements of integer vectors.Nadav Rotem2011-06-041-16/+22
| | | | | | | | | (only happens when using the -promote-elements option). The correct legalization order is to first try to promote element. Next, we try to widen vectors. llvm-svn: 132648
* Switch AllocationOrder to using RegisterClassInfo instead of a BitVectorJakob Stoklund Olesen2011-06-035-22/+18
| | | | | | | | | of reserved registers. Use RegisterClassInfo in RABasic as well. This slightly changes som allocation orders because RegisterClassInfo puts CSR aliases last. llvm-svn: 132581
* Preserve the original ordering when a CSR has multiple aliases.Jakob Stoklund Olesen2011-06-031-2/+14
| | | | | | | | Previously, these aliases would be ordered alphabetically. (BH, BL) Print out the computed allocation orders. llvm-svn: 132580
* Add a TODO about memory operands.Eric Christopher2011-06-031-1/+5
| | | | llvm-svn: 132559
* Avoid calling TRI->getAllocatableSet in RAFast.Jakob Stoklund Olesen2011-06-022-9/+23
| | | | | | | | | | | | | | When compiling a program with lots of small functions like 483.xalancbmk, this makes RAFast 11% faster. Add some comments to clarify the difference between unallocatable and reserved registers. It's quite subtle. The fast register allocator depends on EFLAGS' not being allocatable on x86. That way it can completely avoid tracking liveness, and it won't mind when there are multiple uses of a single def. llvm-svn: 132514
* Have LowerOperandForConstraint handle multiple character constraints.Eric Christopher2011-06-022-3/+7
| | | | | | Part of rdar://9119939 llvm-svn: 132510
* Make it possible to have unallocatable register classes.Jakob Stoklund Olesen2011-06-021-0/+2
| | | | | | | | | | | | | | | Some register classes are only used for instruction operand constraints. They should never be used for virtual registers. Previously, those register classes were given an empty allocation order, but now you can say 'let isAllocatable=0' in the register class definition. TableGen calculates if a register is part of any allocatable register class, and makes that information available in TargetRegisterDesc::inAllocatableClass. The goal here is to eliminate use cases for overriding allocation_order_* methods. llvm-svn: 132508
* Just use a SmallVector.Jakob Stoklund Olesen2011-06-022-2/+3
| | | | | | | | | I was confused whether new uint8_t[] would zero-initialize the returned array, and it seems that so is gcc-4.0. This should fix the test failures on darwin 9. llvm-svn: 132500
* Remove dead code.Devang Patel2011-06-021-8/+3
| | | | llvm-svn: 132488
* Update DBG_VALUEs while breaking anti dependencies.Devang Patel2011-06-028-29/+42
| | | | llvm-svn: 132487
* During post RA scheduling, do not try to chase reg defs. to preserve ↵Devang Patel2011-06-022-39/+32
| | | | | | | | DBG_VALUEs. This approach has several downsides, for example, it does not work when dbg value is a constant integer, it does not work if reg is defined more than once, it places end of debug value range markers in the wrong place. It even causes misleading incorrect debug info when duplicate DBG_VALUE instructions point to same reg def. Instead, use simpler approach and let DBG_VALUE follow its predecessor instruction. After live debug value analysis pass, all DBG_VALUE instruction are placed at the right place. Thanks Jakob for the hint! llvm-svn: 132483
* Revert 132424 to fix PR10068.Rafael Espindola2011-06-021-5/+4
| | | | llvm-svn: 132479
* Use RegisterClassInfo::getOrder in RAFast.Jakob Stoklund Olesen2011-06-021-10/+7
| | | | | | | This saves two virtual function calls and an Allocatable BitVector test, making RAFast run 2% faster. llvm-svn: 132471
* Start with a zeroed CSRNum map.Benjamin Kramer2011-06-021-1/+1
| | | | | | Found by valgrind. llvm-svn: 132457
* Initialize members to fix problem found by valgrind.Jakob Stoklund Olesen2011-06-021-2/+3
| | | | llvm-svn: 132456
* Use TRI::has{Sub,Super}ClassEq() where possible.Jakob Stoklund Olesen2011-06-023-4/+3
| | | | | | No functional change. llvm-svn: 132455
* Add a RegisterClassInfo class that lazily caches information aboutJakob Stoklund Olesen2011-06-025-11/+215
| | | | | | | | | | | | | | | | | | | | | | | | | register classes. It provides information for each register class that cannot be determined statically, like: - The number of allocatable registers in a class after filtering out the reserved and invalid registers. - The preferred allocation order with registers that overlap callee-saved registers last. - The last callee-saved register that overlaps a given physical register. This information usually doesn't change between functions, so it is reused for compiling multiple functions when possible. The many possible combinations of reserved and callee saves registers makes it unfeasible to compute this information statically in TableGen. Use RegisterClassInfo to count available registers in various heuristics in SimpleRegisterCoalescing, making the pass run 4% faster. llvm-svn: 132450
* A DBG_VALUE that truncates a range does not start another dbg value range.Devang Patel2011-06-011-0/+5
| | | | llvm-svn: 132433
* Do not drop constant values when a variable's content is described using ↵Devang Patel2011-06-012-14/+47
| | | | | | .debug_loc entries. llvm-svn: 132427
* Recommit 132404 with fixes. rdar://problem/5993888Stuart Hastings2011-06-011-4/+5
| | | | llvm-svn: 132424
* Allow bitcasts between valid types of the same size and vectorEric Christopher2011-06-011-0/+6
| | | | | | | | types if the vector type is legal. Fixes rdar://9306086 llvm-svn: 132420
* Refactor LegalizeTypes: Erase LegalizeAction and make the type legalizer useNadav Rotem2011-06-015-96/+71
| | | | | | the TargetLowering enum. llvm-svn: 132418
* Revert r132358 "Simplify the eviction policy by making the failsafe explicit."Jakob Stoklund Olesen2011-06-011-97/+44
| | | | | | | This commit caused regressions in i386 flops-[568], matrix, salsa20, 256.bzip2, and enc-md5. llvm-svn: 132413
* Fix double FGETSIGN to work on x86_32; followup to 132396.Stuart Hastings2011-06-011-3/+6
| | | | | | rdar://problem/5660695 llvm-svn: 132411
* Turn on FGETSIGN for x86. Followup to 132388. rdar://problem/5660695Stuart Hastings2011-06-011-6/+2
| | | | llvm-svn: 132396
* This patch is another step in the direction of adding vector select. In thisNadav Rotem2011-06-011-1/+28
| | | | | | | | | patch we add a flag to enable a new type legalization decision - to promote integer elements in vectors. Currently, the rest of the codegen does not support this kind of legalization. This flag will be removed when the transition is complete. llvm-svn: 132394
* Add an issue width check to the postRA scheduler. Patch by Max Kazakov!Andrew Trick2011-06-011-0/+6
| | | | | | | | | | For targets with no itinerary (x86) it is a nop by default. For targets with issue width already expressed in the itinerary (ARM) it bypasses a scoreboard check but otherwise does not affect the schedule. It does make the code more consistent and complete and allows new targets to specify their issue width in an arbitrary way. llvm-svn: 132385
* The ARM stuff already calls the Resume function, not the Resume_or_Rethrow. ItBill Wendling2011-06-011-4/+1
| | | | | | | | | | | | | turns out that it could cause an infinite loop in some situations. If this code is triggered and it converts a cleanup into a catchall, but that cleanup was in already in a cleanup, then the _Unwind_SjLj_Resume could infinite loop. I.e., the code doesn't consume the exception object and passes it on to _Unwind_SjLj_Resume. But _USjLjR expects it to be consumed (since it's landing at a catchall instead of a cleanup). So it uses the values that are presently there, which are the values that tell it to jump to the fake landing pad. <rdar://problem/9508402> llvm-svn: 132381
* Incomplete type may not have corresponding DIE, so do not check DIEEntry ↵Devang Patel2011-06-012-5/+6
| | | | | | eagerly. llvm-svn: 132377
* Refactor.Devang Patel2011-05-312-10/+9
| | | | llvm-svn: 132373
* Include global types, that are referenced through local variables, in ↵Devang Patel2011-05-312-7/+8
| | | | | | debug_pubtypes list. llvm-svn: 132371
* Simplify the eviction policy by making the failsafe explicit.Jakob Stoklund Olesen2011-05-311-44/+97
| | | | | | | | | | | | | | | | When assigned ranges are evicted, they are put in the RS_Evicted stage and are not allowed to evict anything else. That prevents looping automatically. When evicting ranges just to get a cheaper register, use only spill weights to find the possible candidates. Avoid breaking hints for this purpose, it is not worth it. Start implementing more complex eviction heuristics, guarded by the temporary -complex-eviction flag. The initial version permits a heavier range to be evicted if it doesn't have any uses where the evicting range is live. This makes it a good candidate for live ranfge splitting. llvm-svn: 132358
* Reapply r132245 with a fix for the bug that broke the darwin9/i386 build.Jakob Stoklund Olesen2011-05-303-55/+72
| | | | llvm-svn: 132309
* Emit the handler's data area. For GCC-style exceptions under Win64, theCharles Davis2011-05-301-0/+21
| | | | | | | handler's data area starts with a 4-byte reference to the personality function, followed by the DWARF LSDA. llvm-svn: 132302
* Revert r132245, "Create two BlockInfo entries when a live range is ↵Jakob Stoklund Olesen2011-05-293-71/+55
| | | | | | | | discontinuous through a block." This commit seems to have broken a darwin 9 tester. llvm-svn: 132299
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