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* TypeLegalizer: Add support for passing of vector-promoted types in registers ↵Nadav Rotem2011-06-041-2/+40
| | | | | | (copyFromParts/copyToParts). llvm-svn: 132649
* TypeLegalizer: Fix a bug in the promotion of elements of integer vectors.Nadav Rotem2011-06-041-16/+22
| | | | | | | | | (only happens when using the -promote-elements option). The correct legalization order is to first try to promote element. Next, we try to widen vectors. llvm-svn: 132648
* Switch AllocationOrder to using RegisterClassInfo instead of a BitVectorJakob Stoklund Olesen2011-06-035-22/+18
| | | | | | | | | of reserved registers. Use RegisterClassInfo in RABasic as well. This slightly changes som allocation orders because RegisterClassInfo puts CSR aliases last. llvm-svn: 132581
* Preserve the original ordering when a CSR has multiple aliases.Jakob Stoklund Olesen2011-06-031-2/+14
| | | | | | | | Previously, these aliases would be ordered alphabetically. (BH, BL) Print out the computed allocation orders. llvm-svn: 132580
* Add a TODO about memory operands.Eric Christopher2011-06-031-1/+5
| | | | llvm-svn: 132559
* Avoid calling TRI->getAllocatableSet in RAFast.Jakob Stoklund Olesen2011-06-022-9/+23
| | | | | | | | | | | | | | When compiling a program with lots of small functions like 483.xalancbmk, this makes RAFast 11% faster. Add some comments to clarify the difference between unallocatable and reserved registers. It's quite subtle. The fast register allocator depends on EFLAGS' not being allocatable on x86. That way it can completely avoid tracking liveness, and it won't mind when there are multiple uses of a single def. llvm-svn: 132514
* Have LowerOperandForConstraint handle multiple character constraints.Eric Christopher2011-06-022-3/+7
| | | | | | Part of rdar://9119939 llvm-svn: 132510
* Make it possible to have unallocatable register classes.Jakob Stoklund Olesen2011-06-021-0/+2
| | | | | | | | | | | | | | | Some register classes are only used for instruction operand constraints. They should never be used for virtual registers. Previously, those register classes were given an empty allocation order, but now you can say 'let isAllocatable=0' in the register class definition. TableGen calculates if a register is part of any allocatable register class, and makes that information available in TargetRegisterDesc::inAllocatableClass. The goal here is to eliminate use cases for overriding allocation_order_* methods. llvm-svn: 132508
* Just use a SmallVector.Jakob Stoklund Olesen2011-06-022-2/+3
| | | | | | | | | I was confused whether new uint8_t[] would zero-initialize the returned array, and it seems that so is gcc-4.0. This should fix the test failures on darwin 9. llvm-svn: 132500
* Remove dead code.Devang Patel2011-06-021-8/+3
| | | | llvm-svn: 132488
* Update DBG_VALUEs while breaking anti dependencies.Devang Patel2011-06-028-29/+42
| | | | llvm-svn: 132487
* During post RA scheduling, do not try to chase reg defs. to preserve ↵Devang Patel2011-06-022-39/+32
| | | | | | | | DBG_VALUEs. This approach has several downsides, for example, it does not work when dbg value is a constant integer, it does not work if reg is defined more than once, it places end of debug value range markers in the wrong place. It even causes misleading incorrect debug info when duplicate DBG_VALUE instructions point to same reg def. Instead, use simpler approach and let DBG_VALUE follow its predecessor instruction. After live debug value analysis pass, all DBG_VALUE instruction are placed at the right place. Thanks Jakob for the hint! llvm-svn: 132483
* Revert 132424 to fix PR10068.Rafael Espindola2011-06-021-5/+4
| | | | llvm-svn: 132479
* Use RegisterClassInfo::getOrder in RAFast.Jakob Stoklund Olesen2011-06-021-10/+7
| | | | | | | This saves two virtual function calls and an Allocatable BitVector test, making RAFast run 2% faster. llvm-svn: 132471
* Start with a zeroed CSRNum map.Benjamin Kramer2011-06-021-1/+1
| | | | | | Found by valgrind. llvm-svn: 132457
* Initialize members to fix problem found by valgrind.Jakob Stoklund Olesen2011-06-021-2/+3
| | | | llvm-svn: 132456
* Use TRI::has{Sub,Super}ClassEq() where possible.Jakob Stoklund Olesen2011-06-023-4/+3
| | | | | | No functional change. llvm-svn: 132455
* Add a RegisterClassInfo class that lazily caches information aboutJakob Stoklund Olesen2011-06-025-11/+215
| | | | | | | | | | | | | | | | | | | | | | | | | register classes. It provides information for each register class that cannot be determined statically, like: - The number of allocatable registers in a class after filtering out the reserved and invalid registers. - The preferred allocation order with registers that overlap callee-saved registers last. - The last callee-saved register that overlaps a given physical register. This information usually doesn't change between functions, so it is reused for compiling multiple functions when possible. The many possible combinations of reserved and callee saves registers makes it unfeasible to compute this information statically in TableGen. Use RegisterClassInfo to count available registers in various heuristics in SimpleRegisterCoalescing, making the pass run 4% faster. llvm-svn: 132450
* A DBG_VALUE that truncates a range does not start another dbg value range.Devang Patel2011-06-011-0/+5
| | | | llvm-svn: 132433
* Do not drop constant values when a variable's content is described using ↵Devang Patel2011-06-012-14/+47
| | | | | | .debug_loc entries. llvm-svn: 132427
* Recommit 132404 with fixes. rdar://problem/5993888Stuart Hastings2011-06-011-4/+5
| | | | llvm-svn: 132424
* Allow bitcasts between valid types of the same size and vectorEric Christopher2011-06-011-0/+6
| | | | | | | | types if the vector type is legal. Fixes rdar://9306086 llvm-svn: 132420
* Refactor LegalizeTypes: Erase LegalizeAction and make the type legalizer useNadav Rotem2011-06-015-96/+71
| | | | | | the TargetLowering enum. llvm-svn: 132418
* Revert r132358 "Simplify the eviction policy by making the failsafe explicit."Jakob Stoklund Olesen2011-06-011-97/+44
| | | | | | | This commit caused regressions in i386 flops-[568], matrix, salsa20, 256.bzip2, and enc-md5. llvm-svn: 132413
* Fix double FGETSIGN to work on x86_32; followup to 132396.Stuart Hastings2011-06-011-3/+6
| | | | | | rdar://problem/5660695 llvm-svn: 132411
* Turn on FGETSIGN for x86. Followup to 132388. rdar://problem/5660695Stuart Hastings2011-06-011-6/+2
| | | | llvm-svn: 132396
* This patch is another step in the direction of adding vector select. In thisNadav Rotem2011-06-011-1/+28
| | | | | | | | | patch we add a flag to enable a new type legalization decision - to promote integer elements in vectors. Currently, the rest of the codegen does not support this kind of legalization. This flag will be removed when the transition is complete. llvm-svn: 132394
* Add an issue width check to the postRA scheduler. Patch by Max Kazakov!Andrew Trick2011-06-011-0/+6
| | | | | | | | | | For targets with no itinerary (x86) it is a nop by default. For targets with issue width already expressed in the itinerary (ARM) it bypasses a scoreboard check but otherwise does not affect the schedule. It does make the code more consistent and complete and allows new targets to specify their issue width in an arbitrary way. llvm-svn: 132385
* The ARM stuff already calls the Resume function, not the Resume_or_Rethrow. ItBill Wendling2011-06-011-4/+1
| | | | | | | | | | | | | turns out that it could cause an infinite loop in some situations. If this code is triggered and it converts a cleanup into a catchall, but that cleanup was in already in a cleanup, then the _Unwind_SjLj_Resume could infinite loop. I.e., the code doesn't consume the exception object and passes it on to _Unwind_SjLj_Resume. But _USjLjR expects it to be consumed (since it's landing at a catchall instead of a cleanup). So it uses the values that are presently there, which are the values that tell it to jump to the fake landing pad. <rdar://problem/9508402> llvm-svn: 132381
* Incomplete type may not have corresponding DIE, so do not check DIEEntry ↵Devang Patel2011-06-012-5/+6
| | | | | | eagerly. llvm-svn: 132377
* Refactor.Devang Patel2011-05-312-10/+9
| | | | llvm-svn: 132373
* Include global types, that are referenced through local variables, in ↵Devang Patel2011-05-312-7/+8
| | | | | | debug_pubtypes list. llvm-svn: 132371
* Simplify the eviction policy by making the failsafe explicit.Jakob Stoklund Olesen2011-05-311-44/+97
| | | | | | | | | | | | | | | | When assigned ranges are evicted, they are put in the RS_Evicted stage and are not allowed to evict anything else. That prevents looping automatically. When evicting ranges just to get a cheaper register, use only spill weights to find the possible candidates. Avoid breaking hints for this purpose, it is not worth it. Start implementing more complex eviction heuristics, guarded by the temporary -complex-eviction flag. The initial version permits a heavier range to be evicted if it doesn't have any uses where the evicting range is live. This makes it a good candidate for live ranfge splitting. llvm-svn: 132358
* Reapply r132245 with a fix for the bug that broke the darwin9/i386 build.Jakob Stoklund Olesen2011-05-303-55/+72
| | | | llvm-svn: 132309
* Emit the handler's data area. For GCC-style exceptions under Win64, theCharles Davis2011-05-301-0/+21
| | | | | | | handler's data area starts with a 4-byte reference to the personality function, followed by the DWARF LSDA. llvm-svn: 132302
* Revert r132245, "Create two BlockInfo entries when a live range is ↵Jakob Stoklund Olesen2011-05-293-71/+55
| | | | | | | | discontinuous through a block." This commit seems to have broken a darwin 9 tester. llvm-svn: 132299
* Fix PR10046 by updating LiveVariables kill info when splitting live ranges.Jakob Stoklund Olesen2011-05-291-2/+39
| | | | | | | | | | | | | This only affects targets like Mips where branch instructions may kill virtual registers. Most other targets branch on flag values, so virtual registers are not involved. The problem is that MachineBasicBlock::updateTerminator deletes branches and inserts new ones while LiveVariables keeps a list of pointers to instructions that kill virtual registers. That list wasn't properly updated in MBB::SplitCriticalEdge. llvm-svn: 132298
* When generating against the Win64 EH scheme, set the handler to the GCC-specificCharles Davis2011-05-291-0/+7
| | | | | | | | | | | | | | | | handler. At this moment, only GCC-style exceptions are supported. Other kinds of exceptions, including "traditional" SEH and Microsoft Visual C++ exceptions, need more work--and an compiler exception model that isn't specific to GCC-style exceptions! In particular, I imagine that it would be possible to mix "traditional" SEH with GCC-style EH or Microsoft C++ EH. Currently LLVM has no way (beyond some target-specific defaults and whole-module compiler switches) of knowing which scheme to use when. llvm-svn: 132283
* Refactor the type legalizer. Switch TargetLowering to a new enum - ↵Nadav Rotem2011-05-282-33/+26
| | | | | | | | | | | LegalizeTypeAction. This patch does not change the behavior of the type legalizer. The codegen produces the same code. This infrastructural change is needed in order to enable complex decisions for vector types (needed by the vector-select patch). llvm-svn: 132263
* Erase instructions _after_ checking their type.Benjamin Kramer2011-05-281-3/+4
| | | | llvm-svn: 132256
* Implement and document the llvm.eh.resume intrinsic, which isJohn McCall2011-05-281-25/+42
| | | | | | | | | | | | | | | | | transformed by the inliner into a branch to the enclosing landing pad (when inlined through an invoke). If not so optimized, it is lowered DWARF EH preparation into a call to _Unwind_Resume (or _Unwind_SjLj_Resume as appropriate). Its chief advantage is that it takes both the exception value and the selector value as arguments, meaning that there is zero effort in recovering these; however, the frontend is required to pass these down, which is not actually particularly difficult. Also document the behavior of landing pads a bit better, and make it clearer that it's okay that personality functions don't always land at landing pads. This is just a fact of life. Don't write optimizations that rely on pushing things over an unwind edge. llvm-svn: 132253
* When generating code for Win64 EH, emit StartProc and EndProc directives.Charles Davis2011-05-282-0/+31
| | | | llvm-svn: 132250
* Create two BlockInfo entries when a live range is discontinuous through a block.Jakob Stoklund Olesen2011-05-283-55/+71
| | | | | | | | | | | | | | | | | | | Delete the Kill and Def markers in BlockInfo. They are no longer necessary when BlockInfo describes a continuous live range. This only affects the relatively rare kind of basic block where a live range looks like this: |---x o---| Now live range splitting can pretend that it is looking at two blocks: |---x o---| This allows the code to be simplified a bit. llvm-svn: 132245
* Add SplitAnalysis::getNumLiveBlocks().Jakob Stoklund Olesen2011-05-283-5/+12
| | | | | | | | | | | It is important that this function returns the same number of live blocks as countLiveBlocks(CurLI) because live range splitting uses the number of live blocks to ensure it is making progress. This is in preparation of supporting duplicate UseBlock entries for basic blocks that have a virtual register live-in and live-out, but not live-though. llvm-svn: 132244
* Select DW_AT_const_value size based on global variable size.Devang Patel2011-05-281-5/+13
| | | | llvm-svn: 132239
* Fix the root cause of the bootstrap failure:Rafael Espindola2011-05-281-1/+1
| | | | | | | | There was no way to check if a given register/mode pair was valid. We now return an error code (-2) instead of asserting. If anyone thinks that an assert at this point is really needed, we can autogen a hasValidDwarfRegNum instead. llvm-svn: 132236
* Stub out support for Win64-style exceptions. Note that this is merely usingCharles Davis2011-05-275-0/+99
| | | | | | | the Win64 EH mechanism to implement GCC-style exceptions. LLVM supports hardly anything else at this point! llvm-svn: 132234
* Fix a regression I recently introduced by removing DwarfRegNum ofRafael Espindola2011-05-271-1/+18
| | | | | | | | | | subregisters: When a value is in a subregister, at least report the location as being the superregister. We should extend the .td files to encode the bit range so that we can produce a DW_OP_bit_piece. llvm-svn: 132224
* Make size computation less brittle.Rafael Espindola2011-05-272-30/+6
| | | | llvm-svn: 132222
* Add the suffix to the Win64 EH data sections' names if given. Add a test forCharles Davis2011-05-271-0/+22
| | | | | | this. XFAIL'd, because the COFF AsmParser can't handle .section yet. llvm-svn: 132220
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