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* Fix the ExecutionDepsFix pass to handle AVX instructions.Andrew Trick2013-10-141-22/+93
| | | | | | | | | | | | | | | | | | | | | | | | This pass is needed to break false dependencies. Without it, unlucky register assignment can result in wild (5x) swings in performance. This pass was trying to handle AVX but not getting it right. AVX doesn't have partial register defs, it has unused register reads in which the high bits of a source operand are copied into the unused bits of the dest. Fixing this requires conservative liveness analysis. This is awkard because the pass already has its own pseudo-liveness. However, proper liveness is expensive, and we would like to use a generic utility to compute it. The fix only invokes liveness on-demand. It is rare to detect a case that needs undef-read dependence breaking, but when it happens, it can be needed many times within a very large block. I think the existing heuristic which uses a register window of 16 is too conservative for loop-carried false dependencies. If the loop is a reduction. The out-of-order engine may be able to execute several loop iterations in parallel. However, I'll leave this tuning exercise for next time. llvm-svn: 192635
* LiveRegUnits: Use *MBB for consistency and convenience.Andrew Trick2013-10-142-9/+9
| | | | llvm-svn: 192634
* LiveRegUnits::removeRegsInMask safety.Andrew Trick2013-10-141-10/+19
| | | | | | | | | Clobbering is exclusive not inclusive on register units. For liveness, we need to consider all the preserved registers. e.g. A regmask that clobbers YMM0 may preserve XMM0. Units are only clobbered when all super-registers are clobbered. llvm-svn: 192623
* Use a SparseSet in LiveRegUnits.Andrew Trick2013-10-141-19/+18
| | | | | | | | | | Some clients may add block live ins and may track liveness over a large scope. This guarantees an efficient implementation in all cases with no memory allocation/deallocation, independent of the number of target registers. It could be slightly less convenient but is fine in the expected case. llvm-svn: 192622
* Move LiveRegUnits implementation into .cpp. Comment and format.Andrew Trick2013-10-142-0/+103
| | | | llvm-svn: 192621
* Convert LiveRegUnits methods to the current convention (it's new code).Andrew Trick2013-10-141-12/+12
| | | | llvm-svn: 192619
* Debug Info: static member DIE creation.Manman Ren2013-10-142-14/+24
| | | | | | | | | | | | | Clean up creation of static member DIEs. We can create static member DIEs from two places, so we call getOrCreateStaticMemberDIE from the two places. getOrCreateStaticMemberDIE will get or create the context DIE first, then it will check if the DIE already exists, if not, we create the static member DIE and add it to the context. Creation of static member DIEs are handled in a similar way as subprogram DIEs. llvm-svn: 192618
* Fix indenting.David Blaikie2013-10-141-7/+8
| | | | | | That wasn't confusing /at all/... llvm-svn: 192617
* MachineSink: Fix and tweak critical-edge breaking heuristic.Will Dietz2013-10-141-7/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Per original comment, the intention of this loop is to go ahead and break the critical edge (in order to sink this instruction) if there's reason to believe doing so might "unblock" the sinking of additional instructions that define registers used by this one. The idea is that if we have a few instructions to sink "together" breaking the edge might be worthwhile. This commit makes a few small changes to help better realize this goal: First, modify the loop to ignore registers defined by this instruction. We don't sink definitions of physical registers, and sinking an SSA definition isn't going to unblock an upstream instruction. Second, ignore uses of physical registers. Instructions that define physical registers are rejected for sinking, and so moving this one won't enable moving any defining instructions. As an added bonus, while virtual register use-def chains are generally small due to SSA goodness, iteration over the uses and definitions (used by hasOneNonDBGUse) for physical registers like EFLAGS can be rather expensive in practice. (This is the original reason for looking at this) Finally, to keep things simple continue to only consider this trick for registers that have a single use (via hasOneNonDBGUse), but to avoid spuriously breaking critical edges only do so if the definition resides in the same MBB and therefore this one directly blocks it from being sunk as well. If sinking them together is meant to be, let the iterative nature of this pass sink the definition into this block first. Update tests to accomodate this change, add new testcase where sinking avoids pipeline stalls. llvm-svn: 192608
* Remove the now unused strong phi elimination pass.Rafael Espindola2013-10-144-841/+3
| | | | llvm-svn: 192604
* Fixed a bug in dynamic allocation memory on stack.Elena Demikhovsky2013-10-141-3/+3
| | | | | | | | The alignment of allocated space was wrong, see Bugzila 17345. Done by Zvi Rackover <zvi.rackover@intel.com>. llvm-svn: 192573
* TargetLowering: Don't index into empty string.Will Dietz2013-10-131-1/+1
| | | | | | (This is triggered by current lit tests) llvm-svn: 192549
* Debug Info: remove form from function addDIEEntry.Manman Ren2013-10-113-26/+17
| | | | | | | | | The form must be a reference form in addDIEEntry. Which reference form to use will be decided by the callee. No functionality change. llvm-svn: 192517
* fConversion: Attempt #2 at fixing the MSVC build.Benjamin Kramer2013-10-111-2/+2
| | | | llvm-svn: 192492
* IfConversion: Try to unbreak the MSVC build.Benjamin Kramer2013-10-111-1/+1
| | | | llvm-svn: 192487
* Remove kill flags after if conversion if necessaryMatthias Braun2013-10-111-66/+89
| | | | | | | | | | | | | | | | | | | When if converting something like: true: ... = R0<kill> false: ... = R0<kill> then the instructions of the true block must not have a <kill> flag anymore, as the instruction of the false block follow and do still read the R0 value. Specifically this patch determines the set of register live-in in the false block (possibly after simulating the liveness changes of the duplicated instructions). Each of these live-in registers mustn't be killed. llvm-svn: 192482
* [DAGCombiner] Reapply load slicing (192471) with a test that explicitly set ↵Quentin Colombet2013-10-111-2/+574
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sse4.2 support. This should fix the buildbots. Original commit message: [DAGCombiner] Slice a big load in two loads when the element are next to each other in memory and the target has paired load and performs post-isel loads combining. E.g., this optimization will transform something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and performs post-isel loads combining. One should overload TargetLowering::hasPairedLoad to provide this information. The default is false. <rdar://problem/14477220> llvm-svn: 192476
* [DAGCombiner] Revert load slicing (r192471), until I figure out why it fails ↵Quentin Colombet2013-10-111-574/+2
| | | | | | on ubuntu. llvm-svn: 192474
* [DAGCombiner] Slice a big load in two loads when the element are next to eachQuentin Colombet2013-10-111-2/+574
| | | | | | | | | | | | | | | | | | | | | | | | other in memory and the target has paired load and performs post-isel loads combining. E.g., this optimization will transform something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and performs post-isel loads combining. One should overload TargetLowering::hasPairedLoad to provide this information. The default is false. <rdar://problem/14477220> llvm-svn: 192471
* fix typo in commentMatthias Braun2013-10-111-1/+1
| | | | llvm-svn: 192455
* Make AsmPrinter::emitImplicitDef a virtual method so targets can emit custom ↵Justin Holewinski2013-10-111-5/+5
| | | | | | | | | | | | | comments for implicit defs For NVPTX, this fixes a crash where the emitImplicitDef implementation was expecting physical registers, while NVPTX uses virtual registers (with a couple of exceptions). Now, the implicit def comment will be emitted as a true PTX register name. Other targets can use this to customize the output of implicit def comments. Fixes PR17519 llvm-svn: 192444
* LiveRangeCalc.h: Update a description corresponding to r192396. ↵NAKAMURA Takumi2013-10-111-1/+1
| | | | | | [-Wdocumentation] llvm-svn: 192421
* Print register in LiveInterval::print()Matthias Braun2013-10-106-23/+23
| | | | llvm-svn: 192398
* Represent RegUnit liveness with LiveRange instanceMatthias Braun2013-10-1011-113/+116
| | | | | | | Previously LiveInterval has been used, but having a spill weight and register number is unnecessary for a register unit. llvm-svn: 192397
* Work on LiveRange instead of LiveInterval where possibleMatthias Braun2013-10-105-64/+58
| | | | | | | Also change some pointer arguments to references at some places where 0-pointers are not allowed. llvm-svn: 192396
* Change MachineVerifier to work on LiveRange + LiveIntervalMatthias Braun2013-10-101-92/+117
| | | | llvm-svn: 192395
* Pass LiveQueryResult by valueMatthias Braun2013-10-109-21/+24
| | | | | | | This makes the API a bit more natural to use and makes it easier to make LiveRanges implementation details private. llvm-svn: 192394
* Refactor LiveInterval: introduce new LiveRange classMatthias Braun2013-10-102-116/+109
| | | | | | | | | | LiveRange just manages a list of segments and a list of value numbers now as LiveInterval did previously, but without having details like spill weight or a fixed register number. LiveInterval is now a subclass of LiveRange and simply adds the spill weight and the register number. llvm-svn: 192393
* Rename LiveRange to LiveInterval::SegmentMatthias Braun2013-10-1013-240/+242
| | | | | | | | The Segment struct contains a single interval; multiple instances of this struct are used to construct a live range, but the struct is not a live range by itself. llvm-svn: 192392
* Rename parameter: defined regs are not incoming.Matthias Braun2013-10-101-15/+15
| | | | llvm-svn: 192391
* Use getPointerSizeInBits() rather than 8 * getPointerSize()Matt Arsenault2013-10-101-2/+3
| | | | llvm-svn: 192386
* Debug Info: In DIBuilder, the context field of subprogram is updated to useManman Ren2013-10-102-4/+5
| | | | | | | | DIScopeRef. A paired commit at clang is required due to changes to DIBuilder. llvm-svn: 192378
* Debug Info: In DIBuilder, the context and type fields of template_type andManman Ren2013-10-091-3/+4
| | | | | | | | template_value are updated to use DIRef. A paired commit at clang is required due to changes to DIBuilder. llvm-svn: 192320
* Explicitly request unsigned enum types when desiredReid Kleckner2013-10-082-2/+2
| | | | | | | This fixes repeated -Wmicrosoft warnings when self-hosting clang on Windows, and gets us real unsigned enum types with MSVC. llvm-svn: 192227
* Add DbgVariable::resolve per Eric's suggestion.Manman Ren2013-10-082-2/+14
| | | | llvm-svn: 192218
* Debug Info: rename getOriginalTypeSize to getBaseTypeSize.Manman Ren2013-10-081-4/+4
| | | | llvm-svn: 192216
* Debug Info: take advantage of the existing CU::resolve.Manman Ren2013-10-081-7/+7
| | | | llvm-svn: 192215
* Grammar.Eric Christopher2013-10-081-1/+1
| | | | llvm-svn: 192199
* Add a MCTargetStreamer interface.Rafael Espindola2013-10-082-5/+14
| | | | | | | | | | | | | This patch fixes an old FIXME by creating a MCTargetStreamer interface and moving the target specific functions for ARM, Mips and PPC to it. The ARM streamer is still declared in a common place because it is used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are completely hidden in the corresponding Target directories. I will send an email to llvmdev with instructions on how to use this. llvm-svn: 192181
* Formally added an explicit enum for DWARF TLS support. No functionality change.Richard Mitton2013-10-071-3/+4
| | | | llvm-svn: 192118
* Fix some assert messages to say the correct opcode name. Looks like one ↵Craig Topper2013-10-061-7/+7
| | | | | | assert got copy and pasted to many places. llvm-svn: 192078
* Add support for aliases with linkonce_odr.Rafael Espindola2013-10-061-1/+1
| | | | | | This will be used to extend constructor aliases in clang. llvm-svn: 192066
* Emit a better error when running out of registers on inline asm.Benjamin Kramer2013-10-052-4/+6
| | | | | | | | | The most likely case where this error happens is when the user specifies too many register operands. Don't make it look like an internal LLVM bug when we can see that the error is coming from an inline asm instruction. For other instructions we keep the "ran out of registers" error. llvm-svn: 192041
* Remove some really nasty uses of hasRawTextSupport.Rafael Espindola2013-10-051-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When MC was first added, targets could use hasRawTextSupport to keep features working before they were added to the MC interface. The design goal of MC is to provide an uniform api for printing assembly and object files. Short of relaxations and other corner cases, a object file is just another representation of the assembly. It was never the intention that targets would keep doing things like if (hasRawTextSupport()) Set flags in one way. else Set flags in another way. When they do that they create two code paths and the object file is no longer just another representation of the assembly. This also then requires testing with llc -filetype=obj, which is extremelly brittle. This patch removes some of these hacks by replacing them with smaller ones. The ARM flag setting is trivial, so I just moved it to the constructor. For Mips, the patch adds two temporary hack directives that allow the assembly to represent the same things as the object file was already able to. The hope is that the mips developers will replace the hack directives with the same ones that gas uses and drop the -print-hack-directives flag. I will also try to implement a target streamer interface, so that we can move this out of the common code. In summary, for any new work, two rules of the thumb are * Don't use "llc -filetype=obj" in tests. * Don't add calls to hasRawTextSupport. llvm-svn: 192035
* Add OPC_CheckChildSame0-3 to the DAG isel matcher. This replaces sequences ↵Craig Topper2013-10-051-0/+27
| | | | | | of MoveChild, CheckSame, MoveParent. Saves 846 bytes from the X86 DAG isel matcher, ~300 from ARM, ~840 from Hexagon. llvm-svn: 192026
* Debug Info: In DIBuilder, the derived-from field of a DW_TAG_pointer_typeManman Ren2013-10-053-26/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | is updated to use DITypeRef. Move isUnsignedDIType and getOriginalTypeSize from DebugInfo.h to be static helper functions in DwarfCompileUnit. We already have a static helper function "isTypeSigned" in DwarfCompileUnit, and a pointer to DwarfDebug is added to resolve the derived-from field. All three functions need to go across link for derived-from fields, so we need to get hold of a type identifier map. A pointer to DwarfDebug is also added to DbgVariable in order to resolve the derived-from field. Debug info verifier is updated to check a derived-from field is a TypeRef. Verifier will not go across link for derived-from fields, in debug info finder, we go across the link to add derived-from fields to types. Function getDICompositeType is only used by dragonegg and since dragonegg does not generate identifier for types, we use an empty map to resolve the derived-from field. When printing a derived-from field, we use DITypeRef::getName to either return the type identifier or getName of the DIType. A paired commit at clang is required due to changes to DIBuilder. llvm-svn: 192018
* Reorganize some member variables and update a comment.Eric Christopher2013-10-051-6/+6
| | | | llvm-svn: 192017
* Fix one comment and update another. Slightly reformat.Eric Christopher2013-10-052-4/+3
| | | | llvm-svn: 192016
* Add a resolve method on CompileUnit that forwards to DwarfDebug.Eric Christopher2013-10-052-8/+13
| | | | llvm-svn: 192014
* Debug info: Don't crash in SelectionDAGISel when a vreg that is beingAdrian Prantl2013-10-051-3/+7
| | | | | | | | pointed to by a dbg_value belonging to a function argument is eliminated during instruction selection. rdar://problem/15094721. llvm-svn: 192011
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