summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen
Commit message (Collapse)AuthorAgeFilesLines
...
* Refactor ExpandConstantFP so it can optimize load from constpool of types ↵Evan Cheng2008-03-041-16/+19
| | | | | | larger than f64 into extload from smaller types. llvm-svn: 47883
* Did I say 'e = getNumOperands()'? I meant --e, of course.Bill Wendling2008-03-041-1/+1
| | | | llvm-svn: 47875
* Rename isOperand() to isOperandOf() (and other similar methods). It always ↵Evan Cheng2008-03-044-17/+17
| | | | | | confuses me. llvm-svn: 47872
* Miscellaneous clean-ups based on Evan's feedback:Bill Wendling2008-03-032-65/+79
| | | | | | | | | - Cleaned up how the prologue-epilogue inserter loops over the instructions. - Instead of restarting the processing of an instruction if we remove an implicit kill, just update the end iterator and make sure that the iterator isn't incremented. llvm-svn: 47870
* Misc. APInt-ification in the DAGCombiner.Dan Gohman2008-03-031-17/+20
| | | | llvm-svn: 47869
* More APInt-ification.Dan Gohman2008-03-031-10/+6
| | | | llvm-svn: 47868
* Yet more APInt-ification.Dan Gohman2008-03-031-9/+6
| | | | llvm-svn: 47867
* More APInt-ification.Dan Gohman2008-03-031-16/+19
| | | | llvm-svn: 47866
* More APInt-ification.Dan Gohman2008-03-031-3/+4
| | | | llvm-svn: 47864
* Go through the machine instruction's operands to make sure that we're notBill Wendling2008-03-031-12/+52
| | | | | | | marking both a super- and sub-register as "killed". This removes implicit uses that are marked as "killed". llvm-svn: 47862
* Make the register scavenger update the bookkeeping values for sub/superBill Wendling2008-03-031-3/+39
| | | | | | registers. llvm-svn: 47861
* Multiple instructions can be inserted when eliminating frame indexes. We needBill Wendling2008-03-031-7/+24
| | | | | | | the register scavenger to process all of those new instructions instead of just the last one inserted. llvm-svn: 47860
* all but CAS working on x86Andrew Lenharth2008-03-011-13/+14
| | | | llvm-svn: 47798
* Add MVT::is128BitVector and is64BitVector. ShrinkDale Johannesen2008-03-011-16/+5
| | | | | | | unaligned load/store code using them. Per review of unaligned load/store vector patch. llvm-svn: 47782
* Refactor / clean up code; remove td list scheduler special tie breaker (no ↵Evan Cheng2008-03-011-78/+59
| | | | | | real benefit). llvm-svn: 47779
* Don't fill eh frames even though these are text sections.Evan Cheng2008-02-292-8/+9
| | | | llvm-svn: 47765
* If we reload a virtual register that's already been assigned, we want to markBill Wendling2008-02-291-1/+2
| | | | | | that instruction as its "last use". This fixes PR1925. llvm-svn: 47758
* Fix PR2112: don't run loop aligner if target doesn't have a TargetLowering ↵Evan Cheng2008-02-291-3/+5
| | | | | | object. llvm-svn: 47755
* No need for coalescer to update kills. Only copies are coalesced and those ↵Evan Cheng2008-02-292-69/+3
| | | | | | instructions will be deleted. Doh. llvm-svn: 47749
* Remove redundant #include.Evan Cheng2008-02-291-1/+0
| | | | llvm-svn: 47748
* More APInt-ification.Dan Gohman2008-02-291-107/+42
| | | | llvm-svn: 47746
* Use the new convertFromAPInt instead of convertFromZeroExtendedInteger,Dan Gohman2008-02-291-5/+3
| | | | | | | which allows more of the surrounding arithmetic to be done with APInt instead of uint64_t. llvm-svn: 47745
* Use the new APInt-enabled form of getConstant instead of convertingDan Gohman2008-02-291-1/+1
| | | | | | an APInt into a uint64_t to call getConstant. llvm-svn: 47742
* Added option -align-loops=<true/false> to disable loop aligner pass.Evan Cheng2008-02-282-0/+7
| | | | llvm-svn: 47736
* Interface of getByValTypeAlignment differed betweenDale Johannesen2008-02-281-2/+3
| | | | | | | | generic & x86 versions; change generic to follow x86 and improve comments. Add PPC version (not right for non-Darwin.) llvm-svn: 47734
* Fix an assertion message.Dale Johannesen2008-02-281-1/+1
| | | | llvm-svn: 47722
* Keep track how many commutes are performed by the scheduler.Evan Cheng2008-02-281-0/+4
| | | | llvm-svn: 47710
* implement expand for ISD::DECLARE by just deleting it.Chris Lattner2008-02-281-0/+3
| | | | llvm-svn: 47708
* Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to ↵Evan Cheng2008-02-286-10/+92
| | | | | | 16-byte boundaries. llvm-svn: 47703
* Handle load/store of misaligned vectors that are the Dale Johannesen2008-02-271-19/+30
| | | | | | | | | | | | same size as an int type by doing a bitconvert of load/store of the int type (same algorithm as floating point). This makes them work for ppc Altivec. There was some code that purported to handle loads of (some) vectors by splitting them into two smaller vectors, but getExtLoad rejects subvector loads, so this could never have worked; the patch removes it. llvm-svn: 47696
* Fix a bug in dead spill slot elimination.Evan Cheng2008-02-271-0/+2
| | | | llvm-svn: 47687
* Remove the `else', at Evan's insistence.Dan Gohman2008-02-271-2/+1
| | | | llvm-svn: 47686
* Add a FIXME about the VECTOR_SHUFFLE evil hack.Duncan Sands2008-02-271-0/+2
| | | | llvm-svn: 47676
* LegalizeTypes support for EXTRACT_VECTOR_ELT. TheDuncan Sands2008-02-276-59/+363
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | approach taken is different to that in LegalizeDAG when it is a question of expanding or promoting the result type: for example, if extracting an i64 from a <2 x i64>, when i64 needs expanding, it bitcasts the vector to <4 x i32>, extracts the appropriate two i32's, and uses those for the Lo and Hi parts. Likewise, when extracting an i16 from a <4 x i16>, and i16 needs promoting, it bitcasts the vector to <2 x i32>, extracts the appropriate i32, twiddles the bits if necessary, and uses that as the promoted value. This puts more pressure on bitcast legalization, and I've added the appropriate cases. They needed to be added anyway since users can generate such bitcasts too if they want to. Also, when considering various cases (Legal, Promote, Expand, Scalarize, Split) it is a pain that expand can correspond to Expand, Scalarize or Split, so I've changed the LegalizeTypes enum so it lists those different cases - now Expand only means splitting a scalar in two. The code produced is the same as by LegalizeDAG for all relevant testcases, except for 2007-10-31-extractelement-i64.ll, where the code seems to have improved (see below; can an expert please tell me if it is better or not). Before < vs after >. < subl $92, %esp < movaps %xmm0, 64(%esp) < movaps %xmm0, (%esp) < movl 4(%esp), %eax < movl %eax, 28(%esp) < movl (%esp), %eax < movl %eax, 24(%esp) < movq 24(%esp), %mm0 < movq %mm0, 56(%esp) --- > subl $44, %esp > movaps %xmm0, 16(%esp) > pshufd $1, %xmm0, %xmm1 > movd %xmm1, 4(%esp) > movd %xmm0, (%esp) > movq (%esp), %mm0 > movq %mm0, 8(%esp) < subl $92, %esp < movaps %xmm0, 64(%esp) < movaps %xmm0, (%esp) < movl 12(%esp), %eax < movl %eax, 28(%esp) < movl 8(%esp), %eax < movl %eax, 24(%esp) < movq 24(%esp), %mm0 < movq %mm0, 56(%esp) --- > subl $44, %esp > movaps %xmm0, 16(%esp) > pshufd $3, %xmm0, %xmm1 > movd %xmm1, 4(%esp) > movhlps %xmm0, %xmm0 > movd %xmm0, (%esp) > movq (%esp), %mm0 > movq %mm0, 8(%esp) < subl $92, %esp < movaps %xmm0, 64(%esp) --- > subl $44, %esp < movl 16(%esp), %eax < movl %eax, 48(%esp) < movl 20(%esp), %eax < movl %eax, 52(%esp) < movaps %xmm0, (%esp) < movl 4(%esp), %eax < movl %eax, 60(%esp) < movl (%esp), %eax < movl %eax, 56(%esp) --- > pshufd $1, %xmm0, %xmm1 > movd %xmm1, 4(%esp) > movd %xmm0, (%esp) > movd %xmm1, 12(%esp) > movd %xmm0, 8(%esp) < subl $92, %esp < movaps %xmm0, 64(%esp) --- > subl $44, %esp < movl 24(%esp), %eax < movl %eax, 48(%esp) < movl 28(%esp), %eax < movl %eax, 52(%esp) < movaps %xmm0, (%esp) < movl 12(%esp), %eax < movl %eax, 60(%esp) < movl 8(%esp), %eax < movl %eax, 56(%esp) --- > pshufd $3, %xmm0, %xmm1 > movd %xmm1, 4(%esp) > movhlps %xmm0, %xmm0 > movd %xmm0, (%esp) > movd %xmm1, 12(%esp) > movd %xmm0, 8(%esp) llvm-svn: 47672
* LegalizeTypes support for legalizing the maskDuncan Sands2008-02-272-0/+56
| | | | | | | | | | | | | | | | | | | | operand of a VECTOR_SHUFFLE. The mask is a vector of constant integers. The code in LegalizeDAG doesn't bother to legalize the mask, since it's basically just storage for a bunch of constants, however LegalizeTypes is more picky. The problem is that there may not exist any legal vector-of-integers type with a legal element type, so it is impossible to create a legal mask! Unless of course you cheat by creating a BUILD_VECTOR where the operands have a different type to the element type of the vector being built... This is pretty ugly but works - all relevant tests in the testsuite pass, and produce the same assembler with and without LegalizeTypes. llvm-svn: 47670
* LegalizeTypes support for INSERT_VECTOR_ELT.Duncan Sands2008-02-273-6/+47
| | | | llvm-svn: 47669
* Don't track max alignment during stack object allocations since they can be ↵Evan Cheng2008-02-271-2/+1
| | | | | | deleted later. Let PEI compute it. llvm-svn: 47668
* Support for legalizing MEMBARRIER.Duncan Sands2008-02-273-2/+19
| | | | llvm-svn: 47667
* Final de-tabification.Bill Wendling2008-02-272-2/+2
| | | | llvm-svn: 47663
* Spiller now remove unused spill slots.Evan Cheng2008-02-275-22/+108
| | | | llvm-svn: 47657
* Teach Legalize how to expand an EXTRACT_ELEMENT.Dan Gohman2008-02-271-0/+6
| | | | llvm-svn: 47656
* Convert the last remaining users of the non-APInt form ofDan Gohman2008-02-271-35/+15
| | | | | | | ComputeMaskedBits to use the APInt form, and remove the non-APInt form. llvm-svn: 47654
* Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt.Dan Gohman2008-02-272-141/+153
| | | | | | | | Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
* Use a smallvector for inactiveCounts and initialize it lazily Chris Lattner2008-02-261-4/+10
| | | | | | | | instead of init'ing it maximally to zeros on entry. getFreePhysReg is pretty hot and only a few elements are typically used. This speeds up linscan by 5% on 176.gcc. llvm-svn: 47631
* Rename PrintableName to Name.Bill Wendling2008-02-2613-40/+39
| | | | llvm-svn: 47629
* Change "Name" to "AsmName" in the target register info. Gee, a refactoring toolBill Wendling2008-02-2613-41/+44
| | | | | | would have been a Godsend here! llvm-svn: 47625
* Enable -coalescer-commute-instrs by default.Evan Cheng2008-02-261-1/+1
| | | | llvm-svn: 47623
* Avoid aborting on invalid shift counts.Dan Gohman2008-02-261-4/+18
| | | | llvm-svn: 47612
* Fix PR2096, a regression introduced with my patch last night. ThisChris Lattner2008-02-261-1/+1
| | | | | | also fixes cfrac, flops, and 175.vpr llvm-svn: 47605
* Fix a nasty bug in LegalizeTypes (spotted inDuncan Sands2008-02-266-60/+70
| | | | | | | | | | | | | | | | | CodeGen/PowerPC/illegal-element-type.ll): suppose a node X is processed, and processing maps it to a node Y. Then X continues to exist in the DAG, but with no users. While processing some other node, a new node may be created that happens to be equal to X, and thus X will be reused rather than a truly new node. This can cause X to "magically reappear", and since it is in the Processed state in will not be reprocessed, so at the end of type legalization the illegal node X can still be present. The solution is to replace X with Y whenever X gets resurrected like this. llvm-svn: 47601
OpenPOWER on IntegriCloud