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* [DebugInfo] Don't insert DEBUG_VALUE after terminatorsStefan Maksimovic2018-02-091-1/+1
| | | | | | | | | | | | | | r314974 introduced insertion of DEBUG_VALUEs after each redefinition of debug value register in the slot index range. In case the instruction redefining the debug value register was a terminator, machine verifier would complain since it enforces the rule of no non-terminator instructions following the first terminator. Differential Revision: https://reviews.llvm.org/D42801 llvm-svn: 324734
* [SelectionDAG] Provide adequate register class for RegisterSDNodeStefan Maksimovic2018-02-091-1/+16
| | | | | | | | | | When adding operands to machine instructions in case of RegisterSDNodes, generate a COPY node in case the register class does not match the one in the instruction definition. Differental Revision: https://reviews.llvm.org/D35561 llvm-svn: 324733
* [CodeGen] Optimize AccelTablePavel Labath2018-02-091-20/+17
| | | | | | | | | | | | | | | | | Summary: The class contained arrays of two structures (DataArray and HashData). These structures were in 1:1 correspondence, and one of them contained pointers to the other (and *both* contained a "Name" field). By merging these two structures into one, we can save a bit of space without negatively impacting much of anything. Reviewers: JDevlieghere, aprantl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D43073 llvm-svn: 324724
* [GISel]: Verify COPIES involving generic registers.Aditya Nandakumar2018-02-091-0/+30
| | | | | | | | | | | | Add verification for copies involving generic registers if they are compatible - ie if it is a generic copy, then the types are the same, and if a COPY b/w generic and target virtual register, then the sizes should be the same. Only checks if there are no sub registers involved for now. https://reviews.llvm.org/D37775 llvm-svn: 324696
* [CodeGen] Unify the syntax of MBB liveins in MIR and -debug outputFrancis Visoiu Mistrih2018-02-091-5/+12
| | | | | | | | | | | Instead of: Live Ins: %r0 %r1 print: liveins: %r0, %r1 llvm-svn: 324694
* [CodeGen] Don't compute BranchProbability for MBB::printFrancis Visoiu Mistrih2018-02-091-15/+19
| | | | | | | Avoid re-computing BP only to print successor probabilities in -debug printing. llvm-svn: 324690
* [CodeGen] Only print successors when the list is not emptyFrancis Visoiu Mistrih2018-02-091-21/+24
| | | | | | Follow-up of r324685. llvm-svn: 324686
* [CodeGen] Unify the syntax of MBB successors in MIR and -debug outputFrancis Visoiu Mistrih2018-02-091-11/+24
| | | | | | | | | | | Instead of: Successors according to CFG: %bb.6(0x12492492 / 0x80000000 = 14.29%) print: successors: %bb.6(0x12492492); %bb.6(14.29%) llvm-svn: 324685
* [CodeGen] Move printing '\n' from MachineInstr::print to ↵Francis Visoiu Mistrih2018-02-084-8/+13
| | | | | | | | | MachineBasicBlock::print MBB.print wasn't printing it, but the MIRPrinter is printing it. The goal is to unify that as much as possible. llvm-svn: 324681
* Use a stable topological sort in DwarfCompileUnit::createScopeChildrenDIE()Adrian Prantl2018-02-081-13/+67
| | | | | | | | | | | | This addresses review feedback for D42940. The topological sort is slightly more expensive but it can now also detect cycles in the dependencies and actually works correctly. rdar://problem/37217988 Differential Review: https://reviews.llvm.org/D43036 llvm-svn: 324677
* Revert "WIP: [DAGCombiner] Assert that debug info is preserved"Vedant Kumar2018-02-081-31/+4
| | | | | | This reverts commit r324648. It was committed accidentally. llvm-svn: 324650
* WIP: [DAGCombiner] Assert that debug info is preservedVedant Kumar2018-02-081-4/+31
| | | | llvm-svn: 324648
* [SelectionDAG] Add a helper function for creating a boolean constant based ↵Craig Topper2018-02-082-82/+82
| | | | | | | | | | | | | on the target's boolean content Many in SimplifySetCC and FoldSetCC try to create true or false constants. Some of them query getBooleanContents to figure out whether to use all ones or just 1 for true. But many places do not check and just use 1 without ensuring the VT has an i1 scalar type. Note sure if those places only trigger before type legalization so they only see an i1 type? To cleanup the inconsistency and reduce some duplicated code, this patch adds a getBoolConstant method to SelectionDAG that takes are of querying getBooleanContents and doing the right thing. Differential Revision: https://reviews.llvm.org/D43037 llvm-svn: 324634
* [DAGCombiner] Fix a couple mistakes from r324311 by really passing the ↵Craig Topper2018-02-081-2/+4
| | | | | | | | | | original load to ExtendSetCCUses. We're passing the binary op that uses the load instead of the load. Noticed by inspection. Not sure how to test this because this just prevents the introduction of an extend that will later be truncated and will probably be combined out. llvm-svn: 324568
* [DAGCombiner] Don't create truncate nodes in (aext (zextload x)) -> ↵Craig Topper2018-02-081-15/+5
| | | | | | | | (zextload x) and similar folds. NFCI The truncate is being used to replace other users of of the load, but we checked that the load only has one use so there are no other uses to replace. llvm-svn: 324567
* [CodeGen] Print MachineBasicBlock labels using MIR syntax in -debug outputFrancis Visoiu Mistrih2018-02-081-13/+33
| | | | | | | | | | | | | | Instead of: %bb.1: derived from LLVM BB %for.body print: bb.1.for.body: Also use MIR syntax for MBB attributes like "align", "landing-pad", etc. llvm-svn: 324563
* [DAGCombiner] Avoid creating truncate nodes in (zext (and (load)))->(and ↵Craig Topper2018-02-081-22/+25
| | | | | | | | (zextload)) fold until we know for sure we're going to need it. NFCI The truncate is only needed if the load has additional users. It used to get passed to extendSetCCUses so was created early, but that's no longer the case. llvm-svn: 324562
* [DAGCombiner] Rename variable to be slightly better. NFCCraig Topper2018-02-081-21/+21
| | | | | | We were calling a load LN0 but it came from N0.getOperand(0) so its really more like LN00 if we follow the name used in other places. llvm-svn: 324561
* Revert "[DebugInfo] Improvements to representation of enumeration types ↵Momchil Velikov2018-02-071-11/+8
| | | | | | | | (PR36168)" Revert commit r324489, it broke LLDB tests. llvm-svn: 324511
* [SelectionDAG] More Aggressibly prune nodes in AddChains. NFCI.Nirav Dave2018-02-071-1/+3
| | | | | | | | Travel all chains paths to first non-tokenfactor node can be exponential work. Add simple redundency check to avoid this. Fixes PR36264. llvm-svn: 324491
* [DebugInfo] Improvements to representation of enumeration types (PR36168)Momchil Velikov2018-02-071-8/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is the LLVM part of fixing the issues, described in https://bugs.llvm.org/show_bug.cgi?id=36168 * The representation of enumerator values in the debug info metadata now contains a boolean flag isUnsigned, which determines how the bits of the value are interpreted. * The DW_TAG_enumeration type DIE now always (for DWARF version >= 3) includes a DW_AT_type attribute, which refers to the underlying integer type, as suggested in DWARFv4 (5.7 Enumeration Type Entries). * The debug info metadata for enumeration type contains (in flags) indication whether this is a C++11 "fixed enum". * For C++11 enumeration with a fixed underlying type, the DIE also includes the DW_AT_enum_class attribute (for DWARF version >= 4). * Encoding of enumerator constants uses DW_FORM_sdata for signed values and DW_FORM_udata for unsigned values, as suggested by DWARFv4 (7.5.4 Attribute Encodings). The changes should be backwards compatible: * the isUnsigned attribute is optional and defaults to false. * if the underlying type for the enumeration is not available, the enumerator values are considered signed. * the FixedEnum flag defaults to clear. * the bitcode format for DIEnumerator stores the unsigned flag bit #1 of the first record element, so the format does not change and the zero previously stored there is consistent with the false default for IsUnsigned. Differential Revision: https://reviews.llvm.org/D42734 llvm-svn: 324489
* [MergeICmps] Re-commit rL324317 "Enable the MergeICmps Pass by default."Clement Courbet2018-02-071-5/+4
| | | | | | | | | | | | | | | | | | With fixes from rL324341. Original commit message: [MergeICmps] Enable the MergeICmps Pass by default. Summary: Now that PR33325 is fixed, this should always improve the generated code. Reviewers: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42793 llvm-svn: 324465
* [LegalizeDAG] Truncate condition operand of ISD::SELECTEugene Leviant2018-02-071-1/+6
| | | | | | Differential revision: https://reviews.llvm.org/D42737 llvm-svn: 324447
* [DAGCombiner][AMDGPU][X86] Turn cttz/ctlz into ↵Craig Topper2018-02-061-0/+14
| | | | | | | | | | | | cttz_zero_undef/ctlz_zero_undef if we can prove the input is never zero X86 currently has a late DAG combine after cttz/ctlz are turned into BSR+BSF+CMOV to detect this and remove the CMOV. But we should be able to do this much earlier and avoid creating the cmov all together. For the changed AMDGPU test case it appears that previously the i8 cttz was type legalized to i16 which introduced an OR with 256 in order to limit the result to 8 on the widened type. At this point the result is known to never be zero, but nothing checked that. Then operation legalization is told to promote all i16 cttz to i32. This introduces an extend and a truncate and another OR with 65536 to limit the result to 16. With the DAG combiner change we are able to prevent the creation of the second OR since the opcode will have been changed to cttz_zero_undef after the first OR. I the lack of the OR caused the instruction to change to v_ffbl_b32_sdwa Differential Revision: https://reviews.llvm.org/D42985 llvm-svn: 324427
* Add DWARF for discriminated unionsAdrian Prantl2018-02-062-2/+36
| | | | | | | | | | | | | | | | | | | | | | | | | n Rust, an enum that carries data in the variants is, essentially, a discriminated union. Furthermore, the Rust compiler will perform space optimizations on such enums in some situations. Previously, DWARF for these constructs was emitted using a hack (a magic field name); but this approach stopped working when more space optimizations were added in https://github.com/rust-lang/rust/pull/45225. This patch changes LLVM to allow discriminated unions to be represented in DWARF. It adds createDiscriminatedUnionType and createDiscriminatedMemberType to DIBuilder and then arranges for this to be emitted using DWARF's DW_TAG_variant_part and DW_TAG_variant. Note that DWARF requires that a discriminated union be represented as a structure with a variant part. However, as Rust only needs to emit pure discriminated unions, this is what I chose to expose on DIBuilder. Patch by Tom Tromey! Differential Revision: https://reviews.llvm.org/D42082 llvm-svn: 324426
* [LivePhysRegs] Fix handling of return instructions.Eli Friedman2018-02-061-17/+14
| | | | | | | | | | | | | | | | | See D42509 for the original version of this. Basically, there are two significant changes to behavior here: - addLiveOuts always adds all pristine registers (even if a block has no successors). - addLiveOuts and addLiveOutsNoPristines always add all callee-saved registers for return blocks (including conditional return blocks). I cleaned up the functions a bit to make it clear these properties hold. Differential Revision: https://reviews.llvm.org/D42655 llvm-svn: 324422
* Add SelectionDAGDumper support for strict FP nodesAndrew Kaylor2018-02-061-0/+20
| | | | | | Patch by Kevin P. Neal llvm-svn: 324416
* Fix a crash when emitting DIEs for variable-length arraysAdrian Prantl2018-02-063-33/+50
| | | | | | | | | | | | | VLAs may refer to a previous DIE to express the DW_AT_count of their type. Clang generates an artificial "vla_expr" variable for this. If this DIE hasn't been created yet LLVM asserts. This patch fixes this by sorting the local variables so that dependencies come before they are needed. It also replaces the linear scan in DWARFFile with a std::map, which can be faster. Differential Revision: https://reviews.llvm.org/D42940 llvm-svn: 324412
* [TargetLowering] use local variable to reduce duplication; NFCISanjay Patel2018-02-061-52/+32
| | | | llvm-svn: 324401
* [TargetLowering] use local variables to reduce duplication; NFCISanjay Patel2018-02-061-6/+6
| | | | llvm-svn: 324397
* [DAG, X86] Improve Dependency analysis when doing multi-nodeNirav Dave2018-02-061-215/+80
| | | | | | | | | | | | | | | | | | | | Instruction Selection Cleanup cycle/validity checks in ISel (IsLegalToFold, HandleMergeInputChains) and X86 (isFusableLoadOpStore). Now do a full search for cycles / dependencies pruning the search when topological property of NodeId allows. As part of this propogate the NodeId-based cutoffs to narrow hasPreprocessorHelper searches. Reviewers: craig.topper, bogner Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D41293 llvm-svn: 324359
* Fix unused variable warning in release mode. NFC.Alexander Ivchenko2018-02-061-0/+1
| | | | llvm-svn: 324330
* Revert "[MergeICmps] Enable the MergeICmps Pass by default."Clement Courbet2018-02-061-4/+5
| | | | | | | | Breaks clang-ppc64be-linux-multistage buildbot. This reverts commit 515bab711f308c2e8299c49dd8c84ea6a2e0b60e. llvm-svn: 324319
* [MergeICmps] Enable the MergeICmps Pass by default.Clement Courbet2018-02-061-5/+4
| | | | | | | | | | | | Summary: Now that PR33325 is fixed, this should always improve the generated code. Reviewers: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42793 llvm-svn: 324317
* [DAGCombiner] Pass the original load to ExtendSetCCUses not the turncate.Craig Topper2018-02-061-11/+12
| | | | | | | | | | | | | | | | | | | | | | | Summary: This method is trying to use the truncate node to find which SETCC operand should be replaced directly with the extended load. This used to work correctly because all uses of the original load were replaced by the truncate before this function was called. So this was used to effectively bypass the truncate and find the load under it. All but one of the callers now call this before the truncate has replaced the laod so the setcc doesn't yet use the truncate. To account for this we should pass the original load instead. I changed the order of that one caller to make this work there too. I don't have a test case because this is probably hidden by later DAG combines causing the extend and truncate to cancel out. I assume this way is a little more efficient and matches what was originally intended. Reviewers: RKSimon, spatel, niravd Reviewed By: niravd Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42878 llvm-svn: 324311
* [PEI][NFC] Move StackSize opt-remark code next to -warn-stack codeFrancis Visoiu Mistrih2018-02-051-7/+6
| | | | | | | This allows us to make sure we're always having the same sizes in both remarks and warnings. llvm-svn: 324283
* [SDAG] Legalize all CondCodes by inverting them and/or swapping operandsKrzysztof Parzyszek2018-02-051-12/+19
| | | | | | Differential Revision: https://reviews.llvm.org/D42788 llvm-svn: 324274
* [DAGCombiner] When folding fold (sext/zext (and/or/xor (sextload/zextload ↵Craig Topper2018-02-031-4/+6
| | | | | | | | | | | | | | | | | | | x), cst)) -> (and/or/xor (sextload/zextload x), (sext/zext cst)) make sure we check the legality of the full extended load. Summary: If the load is already an extended load we should be using the memory VT for the legality check, not just the VT of the current extension. I don't have a test case, just noticed it while investigating some load extension improvements. Reviewers: RKSimon, spatel, niravd Reviewed By: niravd Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42783 llvm-svn: 324181
* [SelectionDAG] Don't use simple VT in generic shuffle codeSimon Pilgrim2018-02-031-1/+1
| | | | | | | | Better to assume that any value type may be commuted, not just MVTs. No test case right now, but discovered while investigating possible shuffle combines. llvm-svn: 324179
* [GISel][NFC]: Move RegisterBankInfo::getSizeInBits into TargetRegisterInfo.Aditya Nandakumar2018-02-022-13/+27
| | | | llvm-svn: 324125
* [SelectionDAG] Consider endianness in scalarizeVectorStore().Jonas Paulsson2018-02-021-2/+5
| | | | | | | | | | | | When handling vectors with non byte-sized elements, reverse the order of the elements in the built integer if the target is Big-Endian. SystemZ tests updated. Review: Eli Friedman, Ulrich Weigand. https://reviews.llvm.org/D42786 llvm-svn: 324063
* [SelectionDAG] Add an assert in getNode() for EXTRACT_VECTOR_ELT.Jonas Paulsson2018-02-021-0/+4
| | | | | | | | When getNode() is called to create an EXTRACT_VECTOR_ELT, assert that the result VT is at least as wide as the vector element type. Review: Eli Friedman llvm-svn: 324061
* Fix debug spelling in ResetMachineFunction pass.Amara Emerson2018-02-021-2/+2
| | | | llvm-svn: 324048
* SplitKit: Fix liveness recomputation in some remat cases.Matthias Braun2018-02-022-11/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Example situation: ``` BB0: %0 = ... use %0 ; ... condjump BB1 jmp BB2 BB1: %0 = ... ; rematerialized def from above (from earlier split step) jmp BB2 BB2: ; ... use %0 ``` %0 will have a live interval with 3 value numbers (for the BB0, BB1 and BB2 parts). Now SplitKit tries and succeeds in rematerializing the value number in BB2 (This only works because it is a secondary split so SplitKit is can trace this back to a single original def). We need to recompute all live ranges affected by a value number that we rematerialize. The case that we missed before is that when the value that is rematerialized is at a join (Phi VNI) then we also have to recompute liveness for the predecessor VNIs. rdar://35699130 Differential Revision: https://reviews.llvm.org/D42667 llvm-svn: 324039
* [GlobalISel][Legalizer] Relax a legalization loop detecting assert.Amara Emerson2018-02-011-1/+3
| | | | | | | Legalizing vectors may keep the element type the same but change the number of elements, the assert didn't take this into account. llvm-svn: 324028
* [DAGCombiner] When folding (insert_subvector undef, (bitcast ↵Craig Topper2018-02-011-1/+3
| | | | | | | | | | | | (extract_subvector N1, Idx)), Idx) -> (bitcast N1) make sure that N1 has the same total size as the original output We were only checking the element count, but not the total width. This could cause illegal bitcasts to be created if for example the output was 512-bits, but N1 is 256 bits, and the extraction size was 128-bits. Fixes PR36199 Differential Revision: https://reviews.llvm.org/D42809 llvm-svn: 324002
* [GlobalISel] Fix assert failure when legalizing non-power-2 loads.Amara Emerson2018-02-011-3/+6
| | | | | | | Until we support extending loads properly we're going to fall back for these. We already handle stores in the same way, so this is just being consistent. llvm-svn: 324001
* [CodeView] Class record member counts should include base classes and ...Brock Wyma2018-02-011-0/+2
| | | | | | | | | Increment the field list member count for base classes and virtual base classes. Differential Revision: https://reviews.llvm.org/D41874 llvm-svn: 324000
* [MachineCopyPropagation] Extend pass to do COPY source forwardingGeoff Berry2018-02-012-1/+210
| | | | | | | | | | | | | | | | | | | | | | Summary: This change extends MachineCopyPropagation to do COPY source forwarding and adds an additional run of the pass to the default pass pipeline just after register allocation. This version of this patch uses the newly added MachineOperand::isRenamable bit to avoid forwarding registers is such a way as to violate constraints that aren't captured in the Machine IR (e.g. ABI or ISA constraints). This change is a continuation of the work started in D30751. Reviewers: qcolombet, javed.absar, MatzeB, jonpa, tstellar Subscribers: tpr, mgorny, mcrosier, nhaehnle, nemanjai, jyknight, hfinkel, arsenm, inouehrs, eraman, sdardis, guyblank, fedor.sergeev, aheejin, dschuff, jfb, myatsina, llvm-commits Differential Revision: https://reviews.llvm.org/D41835 llvm-svn: 323991
* [DAGCombiner] filter out denorm inputs when calculating sqrt estimate (PR34994)Sanjay Patel2018-02-011-10/+25
| | | | | | | | | | | | | | | | | | | | | | | As shown in the example in PR34994: https://bugs.llvm.org/show_bug.cgi?id=34994 ...we can return a very wrong answer (inf instead of 0.0) for square root when using a reciprocal square root estimate instruction. Here, I've conditionalized the filtering out of denorms based on the function having "denormal-fp-math"="ieee" in its attributes. The other options for this attribute are 'preserve-sign' and 'positive-zero'. So we don't generate this extra code by default with just '-ffast-math' (because then there's no denormal attribute string at all), but it works if you specify '-ffast-math -fdenormal-fp-math=ieee' from clang. As noted in the review, there may be other problems in clang that affect the results depending on platform (Linux x86 at least), but this should allow creating the desired codegen. Differential Revision: https://reviews.llvm.org/D42323 llvm-svn: 323981
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