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* Silence a bunch of implicit fallthrough warningsAdrian Prantl2017-12-193-1/+3
| | | | llvm-svn: 321114
* [CodeGen] Move printing MO_BlockAddress operands to MachineOperand::printFrancis Visoiu Mistrih2017-12-192-44/+42
| | | | | | | Work towards the unification of MIR and debug output by refactoring the interfaces. llvm-svn: 321113
* [CodeGen] Move printing MO_IntrinsicID operands to MachineOperand::printFrancis Visoiu Mistrih2017-12-192-9/+4
| | | | | | | Work towards the unification of MIR and debug output by refactoring the interfaces. llvm-svn: 321112
* [CodeGen] Move printing MO_IntrinsicID operands to MachineOperand::printFrancis Visoiu Mistrih2017-12-192-15/+5
| | | | | | | | | | Work towards the unification of MIR and debug output by refactoring the interfaces. Also add support for printing with a null TargetIntrinsicInfo and no MachineFunction. llvm-svn: 321111
* [CodeGen] Move printing MO_FPImmediate operands to MachineOperand::printFrancis Visoiu Mistrih2017-12-192-26/+2
| | | | | | | Work towards the unification of MIR and debug output by refactoring the interfaces. llvm-svn: 321110
* [CodeGen] Refactor printOffset from MO and MIRPrinterFrancis Visoiu Mistrih2017-12-192-29/+16
| | | | llvm-svn: 321109
* [CGP] Format. NFCHaicheng Wu2017-12-191-1/+1
| | | | | | Clang-format. llvm-svn: 321107
* TargetLoweringBase: Fix darwinHasSinCos()Matthias Braun2017-12-191-1/+4
| | | | | | | | Another followup to my refactoring in r321036: Turns out we can end up with an x86 darwin target that is not macos (simulator triples can look like i386-apple-ios) so we need the x86/32bit check in all cases. llvm-svn: 321104
* [GlobalISel][Legalizer] Fix crash when trying to lower G_FNEG of fp128 types.Amara Emerson2017-12-191-0/+3
| | | | | | | | | This doesn't add legalizer support, just prevents crashing so that we can gracefully fall back to SDAG. Fixes PR35690. llvm-svn: 321091
* [DAG] Elide overlapping storeNirav Dave2017-12-191-21/+21
| | | | | | | | | | | | | | | | | Summary: Extend overlapping store elision to handle overwrites of stores by larger stores. Nontemporal tests have been modified to add memory dependencies to prevent store elision. Reviewers: craig.topper, rnk, t.p.northover Subscribers: javed.absar, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D40969 llvm-svn: 321089
* [CodeGen] Move printing MO_CFIIndex operands to MachineOperand::printFrancis Visoiu Mistrih2017-12-192-120/+125
| | | | | | | | | | Work towards the unification of MIR and debug output by refactoring the interfaces. Before this patch we printed "<call frame instruction>" in the debug output. llvm-svn: 321084
* TargetLoweringBase: Followup to r321035Matthias Braun2017-12-191-2/+3
| | | | | | | | | I missed some prefixes and the fact that on AArch64 we use "bzero" instead of "__bzero" as on X86 when doing my refactoring in r321035. Improve tests for bzero. llvm-svn: 321046
* TargetLowering: Fix InitLibcallCallingConvs() overriding things set in ↵Matthias Braun2017-12-191-7/+3
| | | | | | | | | | | | | InitLibcalls() I missed the fact that the later called InitLibcallCallingConvs() overrides some things set in InitLibcalls() when I did the refactoring in r321036. Fix by merging InitLibcallCallingConvs() into InitLibcalls() and doing the initialization earlier. llvm-svn: 321045
* TargetLoweringBase: Remove unnecessary watchos exception; NFCMatthias Braun2017-12-181-3/+4
| | | | | | | WatchOS isn't report as iOS (as opposed to tvos) so the exception I added in my last commit wasn't necessary after all. llvm-svn: 321041
* LiveStacks: Rename LiveStack.{h|cpp} to LiveStacks.{h|cpp}; NFCMatthias Braun2017-12-1810-11/+11
| | | | | | Filenames should match the name of the class they contain. llvm-svn: 321037
* X86/AArch64/ARM: Factor out common sincos_stret logic; NFCIMatthias Braun2017-12-181-16/+37
| | | | | | | | | | | Note: - X86ISelLowering: setLibcallName(SINCOS) was superfluous as InitLibcalls() already does it. - ARMISelLowering: Setting libcallnames for sincos/sincosf seemed superfluous as in the darwin case it wouldn't be used while for all other cases InitLibcalls already does it. llvm-svn: 321036
* AArch64/X86: Factor out common bzero logic; NFCMatthias Braun2017-12-181-0/+4
| | | | llvm-svn: 321035
* Recommit "[DWARFv5] Dump an MD5 checksum in the line-table header."Paul Robinson2017-12-181-0/+2
| | | | | | | | | | | Adds missing support for DW_FORM_data16. Update of r320852/r320886, fixing the unittest again, this time use a raw char string for the test data. Differential Revision: https://reviews.llvm.org/D41090 llvm-svn: 321011
* [DAGCombine] Move AND nodes to multiple load leavesSam Parker2017-12-181-0/+144
| | | | | | | | | | | | | Search from AND nodes to find whether they can be propagated back to loads, so that the AND and load can be combined into a narrow load. We search through OR, XOR and other AND nodes and all bar one of the leaves are required to be loads or constants. The exception node then needs to be masked off meaning that the 'and' isn't removed, but the loads(s) are narrowed still. Differential Revision: https://reviews.llvm.org/D41177 llvm-svn: 320962
* [NFC][CodeGen][ExpandMemCmp] Fix documentation.Clement Courbet2017-12-181-3/+2
| | | | llvm-svn: 320960
* [CGP] Fix the handling select inst in complex addressing modeSerguei Katkov2017-12-181-2/+2
| | | | | | | | | | | | | | | When we put the value in select placeholder we must pass the value through simplification tracker due to the value might be already simplified and erased. This is a fix for PR35658. Reviewers: john.brawn, uabelho Reviewed By: john.brawn Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41251 llvm-svn: 320956
* Revert "Recommit "[DWARFv5] Dump an MD5 checksum in the line-table header.""Paul Robinson2017-12-151-2/+0
| | | | | | | This reverts commit 0afef672f63f0e4e91938656bc73424a8c058bfc. Still failing at runtime on bots. llvm-svn: 320888
* Recommit "[DWARFv5] Dump an MD5 checksum in the line-table header."Paul Robinson2017-12-151-0/+2
| | | | | | | | | | | Adds missing support for DW_FORM_data16. Update of r320852, fixing the unittest to use a hand-coded struct instead of std::array to guarantee data layout. Differential Revision: https://reviews.llvm.org/D41090 llvm-svn: 320886
* Fix unused variable in non-assert buildsMatthias Braun2017-12-151-2/+1
| | | | llvm-svn: 320885
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-1572-248/+242
| | | | | | The Function can never be nullptr so we can return a reference. llvm-svn: 320884
* MachineFunction: Slight refactoring; NFCMatthias Braun2017-12-152-16/+17
| | | | | | Slight cleanup/refactor in preparation for upcoming commit. llvm-svn: 320882
* Revert "[DWARFv5] Dump an MD5 checksum in the line-table header."Paul Robinson2017-12-151-2/+0
| | | | | | Unit test fails on some bots. llvm-svn: 320857
* [DWARFv5] Dump an MD5 checksum in the line-table header.Paul Robinson2017-12-151-0/+2
| | | | | | | | Adds missing support for DW_FORM_data16. Differential Revision: https://reviews.llvm.org/D41090 llvm-svn: 320852
* [SelectionDAG][X86] Fix insert_vector_elt lowering for v32i1/v64i1 with ↵Craig Topper2017-12-151-4/+25
| | | | | | | | | | | | | | | | | | | | | | | non-constant index Summary: Currently we don't handle v32i1/v64i1 insert_vector_elt correctly as we fail to look at the number of elements closely and assume it can only be v16i1 or v8i1. We also can't type legalize v64i1 insert_vector_elt correctly on KNL due to the type not being byte addressable as required by the legalizing through memory accesses path requires. For the first issue, the patch now tries to pick a 512-bit register with the correct number of elements and promotes to that. For the second issue, we now extend the vector to a byte addressable type, do the stores to memory, load the two halves, and then truncate the halves back to the original type. Technically since we changed the type, we may not need two loads, but actually checking that is more work and for the v64i1 case we do need them. Reviewers: RKSimon, delena, spatel, zvi Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D40942 llvm-svn: 320849
* [CodeGen] fix documentation comments; NFCSanjay Patel2017-12-151-10/+7
| | | | llvm-svn: 320840
* Fix for bug PR35549 - Repeated schedule comments.Andrew V. Tischenko2017-12-151-8/+16
| | | | | | Differential Revision: https://reviews.llvm.org/D40960 llvm-svn: 320837
* [CodeGen] Print stack object references as %(fixed-)stack.0 in both MIR and ↵Francis Visoiu Mistrih2017-12-152-9/+31
| | | | | | | | | | | | | | debug output Work towards the unification of MIR and debug output by printing `%stack.0` instead of `<fi#0>`, and `%fixed-stack.0` instead of `<fi#-4>` (supposing there are 4 fixed stack objects). Only debug syntax is affected. Differential Revision: https://reviews.llvm.org/D41027 llvm-svn: 320827
* [MIR] Add support for missing CFI directivesFrancis Visoiu Mistrih2017-12-155-13/+154
| | | | | | | | | | | | | | | | | | | The following CFI directives are suported by MC but not by MIR: * .cfi_rel_offset * .cfi_adjust_cfa_offset * .cfi_escape * .cfi_remember_state * .cfi_restore_state * .cfi_undefined * .cfi_register * .cfi_window_save Add support for printing, parsing and update tests. Differential Revision: https://reviews.llvm.org/D41230 llvm-svn: 320819
* Recommit CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.valueYaxun Liu2017-12-152-3/+8
| | | | | | The regression on ppc64 was not due to this commit. llvm-svn: 320788
* [SelectionDAG] Make getNode calls that take an ArrayRef of SDValue for ↵Craig Topper2017-12-151-4/+7
| | | | | | | | | | operands call NewSDValueDbgMsg. This makes it work better with some build_vector and concat_vectors creations. Adjust the NewSDValueDbgMsg in getConstant to avoid duplicating the print when it calls getSplatBuildVector since getSplatBuildVector didn't trigger a print before. llvm-svn: 320783
* [WebAssembly] Implement @llvm.global_ctors and @llvm.global_dtorsSam Clegg2017-12-151-2/+14
| | | | | | | | | | | | | | | Summary: - lowers @llvm.global_dtors by adding @llvm.global_ctors functions which register the destructors with `__cxa_atexit`. - impements @llvm.global_ctors with wasm start functions and linker metadata See [here](https://github.com/WebAssembly/tool-conventions/issues/25) for more background. Subscribers: jfb, dschuff, mgorny, jgravelle-google, aheejin, sunfish Differential Revision: https://reviews.llvm.org/D41211 llvm-svn: 320774
* EmitFuncArgumentDbgValue: Prefer stack slots over registers for stack argumentsAdrian Prantl2017-12-141-7/+7
| | | | | | | | | | | | | | | | | | While investigating LLVM PR22316 (http://llvm.org/bugs/show_bug.cgi?id=22316) I started wondering if it were not always preferable to emit the initial DBG_VALUEs for stack arguments as FI locations instead of describing the first register they get copied into. The advantage of doing this is that the arguments will be available as soon as the stack is setup. As illustrated by the testcase in the PR, the first copy of the FI into a register may be sunk by MachineSink.cpp into a later basic block. By describing the argument on the stack, we nicely circumvent this problem. <rdar://problem/19583723> Differential Revision: https://reviews.llvm.org/D41135 llvm-svn: 320758
* TLI: Allow using PSV for intrinsic mem operandsMatt Arsenault2017-12-142-2/+4
| | | | llvm-svn: 320756
* Fix many -Wsign-compare and -Wtautological-constant-compare warnings.Zachary Turner2017-12-141-1/+1
| | | | | | | | | | | | Most of the -Wsign-compare warnings are due to the fact that enums are signed by default in the MS ABI, while the tautological comparison warnings trigger on x86 builds where sizeof(size_t) is 4 bytes, so N > numeric_limits<unsigned>::max() is always false. Differential Revision: https://reviews.llvm.org/D41256 llvm-svn: 320750
* DAG: Expose all MMO flags in getTgtMemIntrinsicMatt Arsenault2017-12-143-23/+11
| | | | | | | | | | | | | | Rather than adding more bits to express every MMO flag you could want, just directly use the MMO flags. Also fixes using a bunch of bool arguments to getMemIntrinsicNode. On AMDGPU, buffer and image intrinsics should always have MODereferencable set, but currently there is no way to do that directly during the initial intrinsic lowering. llvm-svn: 320746
* Revert CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.valueYaxun Liu2017-12-142-8/+3
| | | | | | This commit might have caused regression on ppc64. Revert it to verify that. llvm-svn: 320712
* Revert "[DAGCombine] Move AND nodes to multiple load leaves"Benjamin Kramer2017-12-141-124/+0
| | | | | | This reverts commit r320679. Causes miscompiles. llvm-svn: 320698
* [CodeGen] Print MCSymbol operands as <mcsymbol sym> in both MIR and debug outputFrancis Visoiu Mistrih2017-12-142-5/+3
| | | | | | | | | Work towards the unification of MIR and debug output by printing `<mcsymbol sym>` instead of `<MCSym=sym>`. Only debug syntax is affected. llvm-svn: 320685
* [CodeGen] Move printing MO_Metadata operands to MachineOperand::printFrancis Visoiu Mistrih2017-12-142-6/+2
| | | | | | | Work towards the unification of MIR and debug output by refactoring the interfaces. llvm-svn: 320684
* [CodeGen] Print live-out register lists as liveout(...) in both MIR and ↵Francis Visoiu Mistrih2017-12-142-18/+20
| | | | | | | | | | | debug output Work towards the unification of MIR and debug output by printing `liveout(...)` instead of `<regliveout>`. Only debug syntax is affected. llvm-svn: 320683
* [CodeGen] Print global addresses as @foo in both MIR and debug outputFrancis Visoiu Mistrih2017-12-142-70/+67
| | | | | | | | | | | | Work towards the unification of MIR and debug output by printing `@foo` instead of `<ga:@foo>`. Also print target flags in the MIR format since most of them are used on global address operands. Only debug syntax is affected. llvm-svn: 320682
* [CodeGen] Print external symbols as $symbol in both MIR and debug outputFrancis Visoiu Mistrih2017-12-142-17/+13
| | | | | | | | | Work towards the unification of MIR and debug output by printing `$symbol` instead of `<es:symbol>`. Only debug syntax is affected. llvm-svn: 320681
* [DAGCombine] Move AND nodes to multiple load leavesSam Parker2017-12-141-0/+124
| | | | | | | | | | | | | | | | | | | | | | | | Recommitting rL319773, which was reverted due to a recursive issue causing timeouts. This happened because I failed to check whether the discovered loads could be narrowed further. In the case of a tree with one or more narrow loads, that could not be further narrowed, as well as a node that would need masking, an AND could be introduced which could then be visited and recombined again with the same load. This could again create the masking load, with would be combined again... We now check that the load can be narrowed so that this process stops. Original commit message: Search from AND nodes to find whether they can be propagated back to loads, so that the AND and load can be combined into a narrow load. We search through OR, XOR and other AND nodes and all bar one of the leaves are required to be loads or constants. The exception node then needs to be masked off meaning that the 'and' isn't removed, but the loads(s) are narrowed still. Differential Revision: https://reviews.llvm.org/D41177 llvm-svn: 320679
* [SelectionDAG][X86] Improve legalization of v32i1 CONCAT_VECTORS of v16i1 ↵Craig Topper2017-12-141-0/+15
| | | | | | | | | | for AVX512F. A v32i1 CONCAT_VECTORS of v16i1 uses promotion to v32i8 to legalize the v32i1. This results in a bunch of extract_vector_elts and a build_vector that ultimately gets scalarized. This patch checks to see if v16i8 is legal and inserts a any_extend to that so that we can concat v16i8 to v32i8 and avoid creating the extracts. llvm-svn: 320674
* [SelectionDAG] When legalizing the result type of CONCAT_VECTORS, take into ↵Craig Topper2017-12-141-3/+8
| | | | | | | | | | account whether the input type also needs to be promoted. If so go ahead and get the promoted input vector to extract from. Previously, we would create a bunch of any_extends of extract_vector_elts with illegal input type that needs to be promoted. The legalization of those extract_vector_elts would then potentially introduce a truncate. So now we have a bunch of any_extends of truncates. By legalizing both parts together we avoid creating these extra nodes. The test changes seem to be because we were previously combining the build_vector with the any_extend before the any_extend got combined with the truncate. llvm-svn: 320669
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