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* For PR950:Reid Spencer2006-11-274-80/+235
| | | | | | | | | | The long awaited CAST patch. This introduces 12 new instructions into LLVM to replace the cast instruction. Corresponding changes throughout LLVM are provided. This passes llvm-test, llvm/test, and SPEC CPUINT2000 with the exception of 175.vpr which fails only on a slight floating point output difference. llvm-svn: 31931
* Global label not handled correctly.Jim Laskey2006-11-201-3/+11
| | | | llvm-svn: 31883
* Fix PR1011 and CodeGen/Generic/2006-11-20-DAGCombineCrash.llChris Lattner2006-11-201-2/+2
| | | | llvm-svn: 31878
* setOperand should not zap the operand list or add implicit operands to anChris Lattner2006-11-201-39/+0
| | | | | | | | | instruction. Doing so breaks the FP stackifier, the alpha branch selector the sparc fpmover. This fixes PR1012 and CodeGen/X86/fp-stack-compare.ll llvm-svn: 31876
* For PR950:Reid Spencer2006-11-201-0/+56
| | | | | | | | First in a series of patches to convert SetCondInst into ICmpInst and FCmpInst using only two opcodes and having the instructions contain their predicate value. Nothing uses these classes yet. More patches to follow. llvm-svn: 31867
* Don't transform in another bad case: if the block is empty, it should beChris Lattner2006-11-181-1/+2
| | | | | | simplified before we do this xform so that our cost model is accurate. llvm-svn: 31864
* Fix another case we *don't* want to do this xform.Chris Lattner2006-11-181-2/+26
| | | | llvm-svn: 31861
* Implement operator<< for machine basic blocks to make it easier to dump them.Chris Lattner2006-11-181-0/+4
| | | | llvm-svn: 31857
* make the previous change more aggressive, moving any block with no fallthrough.Chris Lattner2006-11-181-9/+11
| | | | | | This speeds up yacr2 by 7% on a core2. llvm-svn: 31856
* Minor code layout tweak: if we have something like this:Chris Lattner2006-11-181-0/+50
| | | | | | | | | | | | | | | if (cond) goto BB2 BB1: ... return; BB2: ... Move BB1 to the end of the function so that the code falls through in the non-return case. This has the effect of moving assert (and other no-return call) bodies and return blocks out of loops. llvm-svn: 31855
* Fixing the ENABLE_OPTIMIZED=1 DISABLE_ASSERTIONS=1 build.Jim Laskey2006-11-171-0/+1
| | | | llvm-svn: 31822
* More removal of std::cerr and DEBUG, replacing with DOUT instead.Bill Wendling2006-11-173-65/+72
| | | | llvm-svn: 31806
* Replace std::cerr uses of the "DEBUG" macro with "DOUT" instead. RemovesBill Wendling2006-11-171-29/+27
| | | | | | a #include of iostream. llvm-svn: 31800
* *** empty log message ***Bill Wendling2006-11-161-1/+0
| | | | llvm-svn: 31789
* Match MachineCodeEmitter changes.Evan Cheng2006-11-162-2/+2
| | | | llvm-svn: 31787
* Don't recompute getNumOperands for each iteration.Bill Wendling2006-11-161-1/+1
| | | | llvm-svn: 31783
* Added a new method "CreateNewLiveInterval" which, given a list ofBill Wendling2006-11-161-0/+49
| | | | | | | LiveRanges, creates a new LiveInterval from them. The LiveRanges should have existed already in another LiveInterval, but removed. llvm-svn: 31780
* enable the branch folding pass for the JIT.Chris Lattner2006-11-161-0/+3
| | | | llvm-svn: 31777
* Fix an incorrectly inverted condition.Evan Cheng2006-11-162-2/+1
| | | | llvm-svn: 31773
* Match live variable changes.Evan Cheng2006-11-151-10/+56
| | | | llvm-svn: 31762
* Minor updates.Evan Cheng2006-11-151-4/+4
| | | | llvm-svn: 31761
* A register def can be partially dead when the whole register has use(s) but ↵Evan Cheng2006-11-151-1/+8
| | | | | | a subreg does not. llvm-svn: 31760
* Do away with kill / dead maps. Move kill / dead info onto MI's.Evan Cheng2006-11-151-81/+107
| | | | llvm-svn: 31759
* Simplify IntrinsicLowering and clarify that it is only for use by theChris Lattner2006-11-151-3/+3
| | | | | | CBE and interpreter. llvm-svn: 31755
* remove dead #includeChris Lattner2006-11-151-1/+0
| | | | llvm-svn: 31753
* Matches MachineInstr changes.Evan Cheng2006-11-131-4/+1
| | | | llvm-svn: 31712
* - Let MachineInstr ctors add implicit def and use operands. Other operandsEvan Cheng2006-11-131-16/+113
| | | | | | | | | will be inserted before these operands. If the opcode changes (by setOpcode), the implicit operands are updated as well. - Added IsKill, IsDead fields to MachineOperand in preparation for changes that move kill / dead info to MachineInstr's. llvm-svn: 31711
* Make an assert comment match the tested assertion.Reid Spencer2006-11-111-1/+1
| | | | llvm-svn: 31686
* Add methods to add implicit def use operands to a MI.Evan Cheng2006-11-112-10/+13
| | | | llvm-svn: 31675
* disallow preinc of a frameindex. This is not profitable and causes 2-addrChris Lattner2006-11-111-5/+11
| | | | | | pass to explode. This fixes a bunch of llc-beta failures on ppc last night. llvm-svn: 31661
* reduce indentation by using early exits. No functionality change.Chris Lattner2006-11-111-154/+161
| | | | llvm-svn: 31660
* move big chunks of code out-of-line, no functionality change.Chris Lattner2006-11-111-235/+241
| | | | llvm-svn: 31658
* Fix a dag combiner bug exposed by my recent instcombine patch. This fixesChris Lattner2006-11-101-1/+1
| | | | | | CodeGen/Generic/2006-11-10-DAGCombineMiscompile.ll and PPC gsm/toast llvm-svn: 31644
* Add implicit def / use operands to MachineInstr.Evan Cheng2006-11-105-29/+23
| | | | llvm-svn: 31633
* When forming a pre-indexed store, make sure ptr isn't the same or is a pred ↵Evan Cheng2006-11-101-7/+16
| | | | | | of value being stored. It would cause a cycle. llvm-svn: 31631
* commentateChris Lattner2006-11-101-0/+2
| | | | llvm-svn: 31627
* Don't attempt expensive pre-/post- indexed dag combine if target does not ↵Evan Cheng2006-11-091-1/+18
| | | | | | support them. llvm-svn: 31598
* Add a mechanism to specify whether a target supports a particular indexed ↵Evan Cheng2006-11-091-0/+8
| | | | | | load / store. llvm-svn: 31597
* Rename ISD::MemOpAddrMode to ISD::MemIndexedModeEvan Cheng2006-11-091-2/+2
| | | | llvm-svn: 31596
* Rename ISD::MemOpAddrMode to ISD::MemIndexedModeEvan Cheng2006-11-092-9/+11
| | | | llvm-svn: 31595
* Allows debugging llc self hosted.Jim Laskey2006-11-091-2/+7
| | | | llvm-svn: 31594
* Merging dwarf info to a single compile unit.Jim Laskey2006-11-091-117/+104
| | | | llvm-svn: 31593
* getPostIndexedAddressParts change: passes in load/store instead of its ↵Evan Cheng2006-11-091-3/+1
| | | | | | loaded / stored VT. llvm-svn: 31584
* Remove M_2_ADDR_FLAG.Evan Cheng2006-11-091-2/+0
| | | | llvm-svn: 31583
* Match more post-indexed ops.Evan Cheng2006-11-081-2/+6
| | | | llvm-svn: 31569
* Remove redundant <cmath>.Jim Laskey2006-11-084-4/+0
| | | | llvm-svn: 31561
* Now can re-enable debug label folding.Jim Laskey2006-11-081-3/+0
| | | | llvm-svn: 31549
* - When performing pre-/post- indexed load/store transformation, do not worryEvan Cheng2006-11-081-90/+29
| | | | | | | | about whether the new base ptr would be live below the load/store. Let two address pass split it back to non-indexed ops. - Minor tweaks / fixes. llvm-svn: 31544
* Fixed a minor bug preventing some pre-indexed load / store transformation.Evan Cheng2006-11-081-3/+3
| | | | llvm-svn: 31543
* For PR950:Reid Spencer2006-11-082-42/+16
| | | | | | | | This patch converts the old SHR instruction into two instructions, AShr (Arithmetic) and LShr (Logical). The Shr instructions now are not dependent on the sign of their operands. llvm-svn: 31542
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