| Commit message (Collapse) | Author | Age | Files | Lines |
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llvm-svn: 38534
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llvm-svn: 38525
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with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
llvm-svn: 37644
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and an
implementation for x86.
llvm-svn: 37576
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llvm-svn: 36483
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llvm-svn: 36452
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llvm-svn: 35660
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register more than once.
llvm-svn: 35513
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TID->numOperands.
llvm-svn: 35375
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llvm-svn: 35365
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llvm-svn: 35208
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llvm-svn: 34878
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- Available value use may be deleted (e.g. noop move).
llvm-svn: 34841
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llvm-svn: 34839
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the last use of the targetted register.
llvm-svn: 34773
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last kill should be updated accordingly.
llvm-svn: 34597
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that reuse it.
llvm-svn: 34536
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spiller, its live range has to be extended.
llvm-svn: 34517
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llvm-svn: 34460
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llvm-svn: 34435
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The code sequence before the spiller is something like:
= tMOVrr
%reg1117 = tMOVrr
%reg1078 = tLSLri %reg1117, 2
The it starts spilling:
%r0 = tRestore <fi#5>, 0
%r1 = tRestore <fi#7>, 0
%r1 = tMOVrr %r1<kill>
tSpill %r1, <fi#5>, 0
%reg1078 = tLSLri %reg1117, 2
It restores the value while processing the first tMOVrr. At this point, the
spiller remembers fi#5 is available in %r0. Next it processes the second move.
It restores the source before the move and spills the result afterwards. The
move becomes a noop and is deleted. However, a spill has been inserted and that
should invalidate reuse of %r0 for fi#5 and add reuse of %r1 for fi#5.
Therefore, %reg1117 (which is also assigned fi#5) should get %r1, not %r0.
llvm-svn: 34039
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llvm-svn: 33457
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rejected during its quest to find a suitable reload register. This avoids an infinite loop in case like this:
t1 := op t2, t3
t2 <- assigned r0 for use by the reload but ended up reuse r1
t3 <- assigned r1 for use by the reload but ended up reuse r0
t1 <- desires r1
sees r1 is taken by t2, tries t2's reload register r0
sees r0 is taken by t3, tries t3's reload register r1
sees r1 is taken by t2, tries t2's reload register r0 ...
llvm-svn: 33382
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llvm-svn: 32698
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rework the hacks that had us passing OStream in. We pass in std::ostream*
instead, check for null, and then dispatch to the correct print() method.
llvm-svn: 32636
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llvm-svn: 32593
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If a spillslot value is available in a register, and there is a noop copy that
targets that register, the spiller correctly decide not to invalidate the
spillslot register.
However, even though the noop copy does not clobbers the value. It does start a
new intersecting live range. That means the spillslot register is available for
use but should not be reused for a two-address instruction modref operand which
would clobber the new live range.
When we remove the noop copy, update the available information by clearing the
canClobber bit.
llvm-svn: 32576
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llvm-svn: 32366
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tied to another oeprand, 2) whether is is being tied to by another operand. So
the destination operand of a two-address MI can be correctly identified.
llvm-svn: 32354
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Reverted.
llvm-svn: 32305
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now cerr, cout, and NullStream resp.
llvm-svn: 32298
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llvm-svn: 32296
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constraint. This bug was causing excessive spills.
llvm-svn: 32295
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is 'unsigned'.
llvm-svn: 32279
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llvm-svn: 32098
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llvm-svn: 31806
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there may be other def(s) apart from the use&def two-address operand. We need
to check if the register reuse for a use&def operand may conflicts with another
def. Provide a mean to recover from the conflict if it is detected when the
defs are processed later.
llvm-svn: 31439
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llvm-svn: 31364
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dest / src operands can be tied together.
llvm-svn: 31363
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http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20061009/038518.html
llvm-svn: 30906
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It's turning:
movl -24(%ebp), %esp
subl $16, %esp
movl -24(%ebp), %ecx
into
movl -24(%ebp), %esp
subl $16, %esp
movl %esp, (%esp)
llvm-svn: 30902
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the stack slot. This fixes PR943.
llvm-svn: 30898
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actually *removes* one of the operands, instead of just assigning both operands
the same register. This make reasoning about instructions unnecessarily complex,
because you need to know if you are before or after register allocation to match
up operand #'s with the target description file.
Changing this also gets rid of a bunch of hacky code in various places.
This patch also includes changes to fold loads into cmp/test instructions in
the X86 backend, along with a significant simplification to the X86 spill
folding code.
llvm-svn: 30108
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llvm-svn: 29911
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instructions which define each value#) to simplify and improve the coallescer.
In particular, this patch:
1. Implements iterative coallescing.
2. Reverts an unsafe hack from handlePhysRegDef, superceeding it with a
better solution.
3. Implements PR865, "coallescing" away the second copy in code like:
A = B
...
B = A
This also includes changes to symbolically print registers in intervals
when possible.
llvm-svn: 29862
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MOV R0, R1
MOV R1, R0
the second machine instruction is removed. Added a regression test.
llvm-svn: 29792
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llvm-svn: 29250
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llvm-svn: 29220
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llvm-svn: 28973
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llvm-svn: 28102
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