summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/VirtRegMap.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* GetRegForReload() now keeps track which registers have been considered and ↵Evan Cheng2007-01-191-8/+32
| | | | | | | | | | | | | | rejected during its quest to find a suitable reload register. This avoids an infinite loop in case like this: t1 := op t2, t3 t2 <- assigned r0 for use by the reload but ended up reuse r1 t3 <- assigned r1 for use by the reload but ended up reuse r0 t1 <- desires r1 sees r1 is taken by t2, tries t2's reload register r0 sees r0 is taken by t3, tries t3's reload register r1 sees r1 is taken by t2, tries t2's reload register r0 ... llvm-svn: 33382
* Eliminate static ctors from StatisticsChris Lattner2006-12-191-7/+7
| | | | llvm-svn: 32698
* Added an automatic cast to "std::ostream*" etc. from OStream. We then canBill Wendling2006-12-171-7/+1
| | | | | | | rework the hacks that had us passing OStream in. We pass in std::ostream* instead, check for null, and then dispatch to the correct print() method. llvm-svn: 32636
* Minor clean up.Evan Cheng2006-12-151-2/+3
| | | | llvm-svn: 32593
* Fix a long-standing spiller bug:Evan Cheng2006-12-141-1/+35
| | | | | | | | | | | | | | | | If a spillslot value is available in a register, and there is a noop copy that targets that register, the spiller correctly decide not to invalidate the spillslot register. However, even though the noop copy does not clobbers the value. It does start a new intersecting live range. That means the spillslot register is available for use but should not be reused for a two-address instruction modref operand which would clobber the new live range. When we remove the noop copy, update the available information by clearing the canClobber bit. llvm-svn: 32576
* Move findTiedToSrcOperand to TargetInstrDescriptor.Evan Cheng2006-12-081-2/+2
| | | | llvm-svn: 32366
* Proper fix for PR1037: to determine is a VR is a modref, check 1) whether it isEvan Cheng2006-12-081-2/+4
| | | | | | | tied to another oeprand, 2) whether is is being tied to by another operand. So the destination operand of a two-address MI can be correctly identified. llvm-svn: 32354
* Revision 1.83 causes PR1037.Reid Spencer2006-12-071-2/+1
| | | | | | Reverted. llvm-svn: 32305
* Changed llvm_ostream et all to OStream. llvm_cerr, llvm_cout, llvm_null, areBill Wendling2006-12-071-3/+3
| | | | | | now cerr, cout, and NullStream resp. llvm-svn: 32298
* MI keeps a ptr of TargetInstrDescriptor, use it.Evan Cheng2006-12-071-2/+3
| | | | llvm-svn: 32296
* getOperandConstraint returns -1 if the operand does have the specific ↵Evan Cheng2006-12-071-1/+1
| | | | | | constraint. This bug was causing excessive spills. llvm-svn: 32295
* Detemplatize the Statistic class. The only type it is instantiated withChris Lattner2006-12-061-6/+6
| | | | | | is 'unsigned'. llvm-svn: 32279
* Match TargetInstrInfo changes.Evan Cheng2006-12-011-4/+2
| | | | llvm-svn: 32098
* More removal of std::cerr and DEBUG, replacing with DOUT instead.Bill Wendling2006-11-171-38/+44
| | | | llvm-svn: 31806
* Fixed some spiller bugs exposed by the recent two-address code changes. NowEvan Cheng2006-11-041-21/+53
| | | | | | | | | there may be other def(s) apart from the use&def two-address operand. We need to check if the register reuse for a use&def operand may conflicts with another def. Provide a mean to recover from the conflict if it is detected when the defs are processed later. llvm-svn: 31439
* RenameEvan Cheng2006-11-011-1/+1
| | | | llvm-svn: 31364
* Two-address instructions no longer have to be A := A op C. Now any pair of ↵Evan Cheng2006-11-011-6/+10
| | | | | | dest / src operands can be tied together. llvm-svn: 31363
* restore my previous patch, now that the X86 backend bug has been fixed:Chris Lattner2006-10-121-17/+32
| | | | | | http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20061009/038518.html llvm-svn: 30906
* Backing out Chris' last commit. It's breaking llvm-gcc bootstrapping.Evan Cheng2006-10-121-32/+17
| | | | | | | | | | | | | It's turning: movl -24(%ebp), %esp subl $16, %esp movl -24(%ebp), %ecx into movl -24(%ebp), %esp subl $16, %esp movl %esp, (%esp) llvm-svn: 30902
* If we see a load from a stack slot into a physreg, consider it as providingChris Lattner2006-10-121-17/+32
| | | | | | the stack slot. This fixes PR943. llvm-svn: 30898
* Fix a long-standing wart in the code generator: two-address instruction loweringChris Lattner2006-09-051-55/+44
| | | | | | | | | | | | | | | actually *removes* one of the operands, instead of just assigning both operands the same register. This make reasoning about instructions unnecessarily complex, because you need to know if you are before or after register allocation to match up operand #'s with the target description file. Changing this also gets rid of a bunch of hacky code in various places. This patch also includes changes to fold loads into cmp/test instructions in the X86 backend, along with a significant simplification to the X86 spill folding code. llvm-svn: 30108
* s|llvm/Support/Visibility.h|llvm/Support/Compiler.h|Chris Lattner2006-08-271-1/+1
| | | | llvm-svn: 29911
* Take advantage of the recent improvements to the liveintervals set (trackingChris Lattner2006-08-241-30/+10
| | | | | | | | | | | | | | | | | | | instructions which define each value#) to simplify and improve the coallescer. In particular, this patch: 1. Implements iterative coallescing. 2. Reverts an unsafe hack from handlePhysRegDef, superceeding it with a better solution. 3. Implements PR865, "coallescing" away the second copy in code like: A = B ... B = A This also includes changes to symbolically print registers in intervals when possible. llvm-svn: 29862
* Added a check so that if we have two machine instructions in this formBill Wendling2006-08-211-10/+30
| | | | | | | | | MOV R0, R1 MOV R1, R0 the second machine instruction is removed. Added a regression test. llvm-svn: 29792
* Eliminate data relocations by using NULL instead of global empty list.Jim Laskey2006-07-211-4/+6
| | | | llvm-svn: 29250
* Reduce number of exported symbolsAndrew Lenharth2006-07-201-7/+7
| | | | llvm-svn: 29220
* Shave another 27K off libllvmgcc.dylib with visibility hiddenChris Lattner2006-06-281-4/+7
| | | | llvm-svn: 28973
* Move some methods out of MachineInstr into MachineOperandChris Lattner2006-05-041-8/+8
| | | | llvm-svn: 28102
* Fix a latent bug that my spiller patch last week exposed: we were leavingChris Lattner2006-05-011-0/+4
| | | | | | | | | instructions in the virtregfolded map that were deleted. Because they were deleted, newly allocated instructions could end up at the same address, magically finding themselves in the map. The solution is to remove entries from the map when we delete the instructions. llvm-svn: 28041
* When promoting a load to a reg-reg copy, where the load was a previousChris Lattner2006-05-011-0/+1
| | | | | | | instruction folded with spill code, make sure the remove the load from the virt reg folded map. llvm-svn: 28040
* Remove previous patch, which wasn't quite right.Chris Lattner2006-05-011-18/+12
| | | | llvm-svn: 28039
* Remove temp. option -spiller-check-liveout, it didn't cause any failure nor ↵Evan Cheng2006-05-011-5/+1
| | | | | | performance regressions. llvm-svn: 28029
* Local spiller kills a store if the folded restore is turned into a copy.Evan Cheng2006-04-301-5/+15
| | | | | | | | But this is incorrect if the spilled value live range extends beyond the current BB. It is currently controlled by a temporary option -spiller-check-liveout. llvm-svn: 28024
* Mapping of physregs can make it so that the designated and input physregs areChris Lattner2006-04-281-0/+13
| | | | | | the same. In this case, don't emit a noop copy. llvm-svn: 28008
* When we have a two-address instruction where the input cannot be clobberedChris Lattner2006-04-281-26/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | and is already available, instead of falling back to emitting a load, fall back to emitting a reg-reg copy. This generates significantly better code for some SSE testcases, as SSE has lots of two-address instructions and none of them are read/modify/write. As one example, this change does: pshufd %XMM5, XMMWORD PTR [%ESP + 84], 255 xorps %XMM2, %XMM5 cmpltps %XMM1, %XMM0 - movaps XMMWORD PTR [%ESP + 52], %XMM0 - movapd %XMM6, XMMWORD PTR [%ESP + 52] + movaps %XMM6, %XMM0 cmpltps %XMM6, XMMWORD PTR [%ESP + 68] movapd XMMWORD PTR [%ESP + 52], %XMM6 movaps %XMM6, %XMM0 cmpltps %XMM6, XMMWORD PTR [%ESP + 36] cmpltps %XMM3, %XMM0 - movaps XMMWORD PTR [%ESP + 20], %XMM0 - movapd %XMM7, XMMWORD PTR [%ESP + 20] + movaps %XMM7, %XMM0 cmpltps %XMM7, XMMWORD PTR [%ESP + 4] movapd XMMWORD PTR [%ESP + 20], %XMM7 cmpltps %XMM4, %XMM0 ... which is far better than a store followed by a load! llvm-svn: 28001
* Fix a bug that Evan exposed with some changes he's making, and that wasChris Lattner2006-02-251-9/+23
| | | | | | | | | exposed with a fastcc problem (breaking pcompress2 on x86 with -enable-x86-fastcc). When reloading a reused reg, make sure to invalidate the reloaded reg, and check to see if there are any other pending uses of the same register. llvm-svn: 26369
* Remove debugging printout :)Chris Lattner2006-02-251-5/+6
| | | | | | Add a minor compile time win, no codegen change. llvm-svn: 26368
* Refactor some code from being inline to being out in a new class with methods.Chris Lattner2006-02-251-42/+97
| | | | | | | | This gets rid of two gotos, which is always nice, and also adds some comments. No functionality change, this is just a refactor. llvm-svn: 26367
* Fix VC++ warning.Jeff Cohen2006-02-041-1/+1
| | | | llvm-svn: 25957
* Handle another case exposed on X86.Chris Lattner2006-02-031-0/+4
| | | | llvm-svn: 25949
* Fix a nasty problem on two-address machines in the following situation:Chris Lattner2006-02-031-9/+27
| | | | | | | | | | | | | | | | | | | | | | | | store EAX -> [ss#0] [ss#0] += 1 ... use(EAX) In this case, it is not valid to rewrite this as: store EAX -> [ss#0] EAX += 1 store EAX -> [ss#0] ;;; this would also delete the store above ... use(EAX) ... because EAX is not a dead at that point. Keep track of which registers we are allowed to clobber, and which ones we aren't, and don't clobber the ones we're not supposed to. :) This should resolve the issues on X86 last night. llvm-svn: 25948
* significantly simplify the VirtRegMap code by pulling the SpillSlotsAvailableChris Lattner2006-02-031-70/+98
| | | | | | | | | and PhysRegsAvailable maps out into a new AvailableSpills struct. No functionality change. This paves the way for a bugfix, coming up next. llvm-svn: 25947
* Fix VC++ compilation error caused by using a std::map iterator variable to ↵Jeff Cohen2006-02-031-1/+1
| | | | | | | | receive a std::multimap iterator value. For some reason, GCC doesn't have a problem with this. llvm-svn: 25927
* Remove move copies and dead stuff by not clobbering the result reg of a noop ↵Chris Lattner2006-02-031-12/+21
| | | | | | copy. llvm-svn: 25926
* Simplify some codeChris Lattner2006-02-031-45/+40
| | | | llvm-svn: 25924
* Add code that checks for noop copies, which triggers when either:Chris Lattner2006-02-031-0/+13
| | | | | | | | | | | | 1. a target doesn't know how to fold load/stores into copies, or 2. the spiller rewrites the input to a copy to the same register as the dest instead of to the reloaded reg. This will be moved/improved in the near future, but allows elimination of some ancient x86 hacks. This eliminates 92 copies from SMG2000 on X86 and 163 copies from 252.eon. llvm-svn: 25922
* Physregs may hold multiple stack slot values at the same time. Keep trackChris Lattner2006-02-031-37/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of this, and use it to our advantage (bwahahah). This allows us to eliminate another 60 instructions from smg2000 on PPC (probably significantly more on X86). A common old-new diff looks like this: stw r2, 3304(r1) - lwz r2, 3192(r1) stw r2, 3300(r1) - lwz r2, 3192(r1) stw r2, 3296(r1) - lwz r2, 3192(r1) stw r2, 3200(r1) - lwz r2, 3192(r1) stw r2, 3196(r1) - lwz r2, 3192(r1) + or r2, r2, r2 stw r2, 3188(r1) and - lwz r31, 604(r1) - lwz r13, 604(r1) - lwz r14, 604(r1) - lwz r15, 604(r1) - lwz r16, 604(r1) - lwz r30, 604(r1) + or r31, r30, r30 + or r13, r30, r30 + or r14, r30, r30 + or r15, r30, r30 + or r16, r30, r30 + or r30, r30, r30 Removal of the R = R copies is coming next... llvm-svn: 25919
* Fix a deficiency in the spiller that Evan noticed. In particular, considerChris Lattner2006-02-021-1/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this code: store [stack slot #0], R10 = add R14, [stack slot #0] The spiller didn't know that the store made the value of [stackslot#0] available in R10 *IF* the store came from a copy instruction with the store folded into it. This patch teaches VirtRegMap to look at these stores and recognize the values they make available. In one case Evan provided, this code: divsd %XMM0, %XMM1 movsd %XMM1, QWORD PTR [%ESP + 40] 1) movsd QWORD PTR [%ESP + 48], %XMM1 2) movsd %XMM1, QWORD PTR [%ESP + 48] addsd %XMM1, %XMM0 3) movsd QWORD PTR [%ESP + 48], %XMM1 movsd QWORD PTR [%ESP + 4], %XMM0 turns into: divsd %XMM0, %XMM1 movsd %XMM1, QWORD PTR [%ESP + 40] addsd %XMM1, %XMM0 3) movsd QWORD PTR [%ESP + 48], %XMM1 movsd QWORD PTR [%ESP + 4], %XMM0 In this case, instruction #2 was removed because of the value made available by #1, and inst #1 was later deleted because it is now never used before the stack slot is redefined by #3. This occurs here and there in a lot of code with high spilling, on PPC most of the removed loads/stores are LSU-reject-causing loads, which is nice. On X86, things are much better (because it spills more), where we nuke about 1% of the instructions from SMG2000 and several hundred from eon. More improvements to come... llvm-svn: 25917
* Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far ↵Chris Lattner2006-02-021-2/+3
| | | | | | more logical place. Other methods should also be moved if anyoneis interested. :) llvm-svn: 25913
* Add explicit #includes of <iostream>Chris Lattner2006-01-221-0/+1
| | | | llvm-svn: 25515
OpenPOWER on IntegriCloud