| Commit message (Collapse) | Author | Age | Files | Lines |
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This introduces a new pass, SlotIndexes, which is responsible for numbering
instructions for register allocation (and other clients). SlotIndexes numbering
is designed to match the existing scheme, so this patch should not cause any
changes in the generated code.
For consistency, and to avoid naming confusion, LiveIndex has been renamed
SlotIndex.
The processImplicitDefs method of the LiveIntervals analysis has been moved
into its own pass so that it can be run prior to SlotIndexes. This was
necessary to match the existing numbering scheme.
llvm-svn: 85979
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get FixedStack PseudoSourceValues.
llvm-svn: 84326
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llvm-svn: 79842
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LiveInterval, etc to raw_ostream.
llvm-svn: 76965
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- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.
Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0
If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.
- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.
This is work in progress, not yet enabled.
llvm-svn: 73381
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MachineRegisterInfo. This allows more passes to set them.
llvm-svn: 73346
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class.
llvm-svn: 70821
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not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However, reloads and restores might be folded into uses / defs and freed registers might not be used at all.
VirtRegMap keeps track of allocations so it knows what's not used. As a horrible hack, the stack coloring can color spill slots with *free* registers. That is, it replace reload and spills with copies from and to the free register. It unfold instructions that load and store the spill slot and replace them with register using variants.
Not yet enabled. This is part 1. More coming.
llvm-svn: 70787
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llvm-svn: 68099
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llvm-svn: 68092
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llvm-svn: 67000
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llvm-svn: 66870
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No (intended) functionality change.
llvm-svn: 66720
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the same instruction as kill. This fixes PR3706.
llvm-svn: 66428
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llvm-svn: 66363
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llvm-svn: 65679
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already marked livein.
llvm-svn: 65498
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Sorry, it's impossible to reduce a sensible test case. It basically requires the moon and stars to align in order to cause a failure.
llvm-svn: 65497
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exposed by recent availability fallthrough changes.
llvm-svn: 64745
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llvm-svn: 64428
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the new way, where all of the information is passed on SDNodes and machine
instructions.
llvm-svn: 64427
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llvm-svn: 64381
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basic blocks, e.g. x86 fp stack registers.
llvm-svn: 64374
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registers to live-in set.
llvm-svn: 64372
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a previous instruction.
llvm-svn: 64339
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availability information over BB boundaries. It visits BB's in depth first order. After visiting a BB if it find a successor which has a single predecessor it visits the successor next without clearing the availability information. This allows the successor to omit reloads or change them into copies.
llvm-svn: 64298
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llvm-svn: 63599
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sub-register indices as well.
llvm-svn: 62600
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llvm-svn: 60392
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reuse happened.
Patch by Lang Hames!
llvm-svn: 57720
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of aliases.
llvm-svn: 57673
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instead of requiring all "short description" strings to begin with
two spaces. This makes these strings less mysterious, and it fixes
some cases where short description strings mistakenly did not
begin with two spaces.
llvm-svn: 57521
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ENABLE_EXPENSIVE_CHECKS for finding this.
llvm-svn: 57181
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isReg, etc., from isRegister, etc.
llvm-svn: 57006
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llvm-svn: 56085
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on machine operands.
llvm-svn: 56065
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it may be killed by an implicit super-register use.
llvm-svn: 55762
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llvm-svn: 54968
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llvm-svn: 54375
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llvm-svn: 53766
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MachineMemOperands. The pools are owned by MachineFunctions.
This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.
llvm-svn: 53212
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llvm-svn: 52450
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llvm-svn: 52309
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hits 410 times on 444.namd and 122 times on 252.eon.
llvm-svn: 52266
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llvm-svn: 51932
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llvm-svn: 51465
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generated by the spiller.
llvm-svn: 51439
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If local spiller optimization turns some instruction into an identity copy, it will be removed. If the output register happens to be dead (and source is obviously killed), transfer the kill / dead information to last use / def in the same MBB.
llvm-svn: 51306
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several things that were neither in an anonymous namespace nor static
but not intended to be global.
llvm-svn: 51017
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%ecx = op
store %cl<kill>, (addr)
(addr) = op %al
It's not safe to unfold the last operand and eliminate store even though %cl is marked kill. It's a sub-register use which means one of its super-register(s) may be used below.
llvm-svn: 50794
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