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path: root/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
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* Teach two-address pass to update the "source" map so it doesn't perform aEvan Cheng2012-05-181-1/+7
| | | | | | | | | non-profitable commute using outdated info. The test case would still fail because of poor pre-RA schedule. That will be fixed by MI scheduler. rdar://11472010 llvm-svn: 157038
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-071-1/+1
| | | | | | | | | | | | | The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! llvm-svn: 156328
* Fix two-address pass's aggressive instruction commuting heuristics. It's meantEvan Cheng2012-05-031-15/+16
| | | | | | | | | | | | | | | | | | | | | | to catch cases like: %reg1024<def> = MOV r1 %reg1025<def> = MOV r0 %reg1026<def> = ADD %reg1024, %reg1025 r0 = MOV %reg1026 By commuting ADD, it let coalescer eliminate all of the copies. However, there was a bug in the heuristics where it ended up commuting the ADD in: %reg1024<def> = MOV r0 %reg1025<def> = MOV 0 %reg1026<def> = ADD %reg1024, %reg1025 r0 = MOV %reg1026 That did no benefit but rather ensure the last MOV would not be coalesced. rdar://11355268 llvm-svn: 156048
* Added TargetRegisterInfo::getAllocatableClass.Andrew Trick2012-05-031-1/+2
| | | | | | | | | | The ensures that virtual registers always belong to an allocatable class. If your target attempts to create a vreg for an operand that has no allocatable register subclass, you will crash quickly. This ensures that targets define register classes as intended. llvm-svn: 156046
* Patch r153892 for PR11861 apparently broke an external project (see PR12493).Lang Hames2012-04-091-16/+17
| | | | | | | | | | This patch restores TwoAddressInstructionPass's pre-r153892 behaviour when rescheduling instructions in TryInstructionTransform. Hopefully this will fix PR12493. To refix PR11861, lowering of INSERT_SUBREGS is deferred until after the copy that unties the operands is emitted (this seems to be a more appropriate fix for that issue anyway). llvm-svn: 154338
* REG_SEQUENCE expansion to COPY instructions wasn't taking account of sub ↵Pete Cooper2012-04-041-1/+2
| | | | | | register indices on the source registers. No simple test case llvm-svn: 154051
* Remove spurious debug output.Jakob Stoklund Olesen2012-04-041-1/+0
| | | | llvm-svn: 154032
* During two-address lowering, rescheduling an instruction does not untieLang Hames2012-04-021-2/+2
| | | | | | | operands. Make TryInstructionTransform return false to reflect this. Fixes PR11861. llvm-svn: 153892
* RegAlloc superpass: includes phi elimination, coalescing, and scheduling.Andrew Trick2012-02-101-1/+0
| | | | | | | | | | | | | | | | Creates a configurable regalloc pipeline. Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa. When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>. CodeGen transformation passes are never "required" as an analysis ProcessImplicitDefs does not require LiveVariables. We have a plan to massively simplify some of the early passes within the regalloc superpass. llvm-svn: 150226
* whitespaceAndrew Trick2012-02-031-8/+8
| | | | llvm-svn: 149671
* Set correct <def,undef> flags when lowering REG_SEQUENCE.Jakob Stoklund Olesen2012-01-241-0/+46
| | | | | | | | | | | | | | | | | | | | A REG_SEQUENCE instruction is lowered into a sequence of partial defs: %vreg7:ssub_0<def,undef> = COPY %vreg20:ssub_0 %vreg7:ssub_1<def> = COPY %vreg2 %vreg7:ssub_2<def> = COPY %vreg2 %vreg7:ssub_3<def> = COPY %vreg2 The first def needs an <undef> flag to indicate it is the beginning of the live range, while the other defs are read-modify-write. Previously, we depended on LiveIntervalAnalysis to notice and fix the missing <def,undef>, but that solution was never robust, it was causing problems with ProcessImplicitDefs and the lowering of chained REG_SEQUENCE instructions. This fixes PR11841. llvm-svn: 148879
* Preserve <def,undef> flags in CoalesceExtSubRegs.Jakob Stoklund Olesen2012-01-241-3/+7
| | | | | | | This won't have an effect until EliminateRegSequences() starts setting the undef flags. llvm-svn: 148779
* Fix ISD::REG_SEQUENCE to accept physical registers and change ↵Pete Cooper2012-01-181-9/+12
| | | | | | TwoAddressInstructionPass to insert copies for any physical reg operands of the REG_SEQUENCE llvm-svn: 148377
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-18/+13
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* Simplify code. No functionality change.Benjamin Kramer2011-12-031-2/+1
| | | | | | -3% on ARMDissasembler.cpp. llvm-svn: 145773
* Disable expensive two-address optimizations at -O0. rdar://10453055Evan Cheng2011-11-161-0/+8
| | | | llvm-svn: 144806
* Disable the assertion again. Looks like fastisel is still generating bad ↵Evan Cheng2011-11-161-1/+2
| | | | | | kill markers. llvm-svn: 144804
* Revert r144568 now that r144730 has fixed the fast-isel kill marker bug.Evan Cheng2011-11-161-2/+1
| | | | llvm-svn: 144776
* If the 2addr instruction has other kills, don't move it below any other uses ↵Evan Cheng2011-11-161-2/+7
| | | | | | since we don't want to extend other live ranges. llvm-svn: 144772
* RescheduleKillAboveMI() must backtrack to before the rescheduled DBG_VALUE ↵Evan Cheng2011-11-161-1/+1
| | | | | | instructions. rdar://10451185 llvm-svn: 144771
* Process all uses first before defs to accurately capture register liveness. ↵Evan Cheng2011-11-161-7/+13
| | | | | | rdar://10449480 llvm-svn: 144770
* Set SeenStore to true to prevent loads from being moved; also eliminates a ↵Evan Cheng2011-11-151-2/+2
| | | | | | non-deterministic behavior. llvm-svn: 144628
* Avoid dereferencing off the beginning of lists.Evan Cheng2011-11-141-7/+4
| | | | llvm-svn: 144569
* At -O0, multiple uses of a virtual registers in the same BB are being markedEvan Cheng2011-11-141-1/+2
| | | | | | | | "kill". This looks like a bug upstream. Since that's going to take some time to understand, loosen the assertion and disable the optimization when multiple kills are seen. llvm-svn: 144568
* Teach two-address pass to re-schedule two-address instructions (or the killEvan Cheng2011-11-141-19/+356
| | | | | | | | | instructions of the two-address operands) in order to avoid inserting copies. This fixes the few regressions introduced when the two-address hack was disabled (without regressing the improvements). rdar://10422688 llvm-svn: 144559
* PR10998: It is not legal to sink an instruction past the terminator of a ↵Eli Friedman2011-09-231-1/+9
| | | | | | block; make sure we don't do that. llvm-svn: 140428
* Add an isSSA() flag to MachineRegisterInfo.Jakob Stoklund Olesen2011-07-291-0/+3
| | | | | | | | | | | | | This flag is true from isel to register allocation when the machine function is required to be in SSA form. The TwoAddressInstructionPass and PHIElimination passes clear the flag. The SSA flag wil be used by the machine code verifier to check for SSA form, and eventually an assertion can enforce it in +Asserts builds. This will catch the common target error of creating machine code with multiple defs of a virtual register. llvm-svn: 136532
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-16/+17
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.Evan Cheng2011-06-271-1/+1
| | | | llvm-svn: 133944
* Simplify code. No change in functionality.Benjamin Kramer2011-06-181-6/+1
| | | | llvm-svn: 133350
* Fix an issue where the two-address conversion pass incorrectly rewrites untiedCameron Zwarich2011-06-071-9/+16
| | | | | | operands to an early clobber register. This fixes <rdar://problem/9566076>. llvm-svn: 132738
* Catch more cases where 2-address pass should 3-addressify instructions. ↵Evan Cheng2011-03-021-49/+70
| | | | | | rdar://9002648. llvm-svn: 126811
* After 3-addressifying a two-address instruction, update the register maps; ↵Evan Cheng2011-02-101-4/+9
| | | | | | add a missing check when considering whether it's profitable to commute. rdar://8977508. llvm-svn: 125259
* Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.Jakob Stoklund Olesen2011-01-101-1/+1
| | | | | | | | These functions not longer assert when passed 0, but simply return false instead. No functional change intended. llvm-svn: 123155
* Shrink a BitVector that didn't mean to store bits for all physical registers.Jakob Stoklund Olesen2011-01-091-6/+4
| | | | llvm-svn: 123108
* Do not model all INLINEASM instructions as having unmodelled side effects.Evan Cheng2011-01-071-1/+1
| | | | | | | | | | Instead encode llvm IR level property "HasSideEffects" in an operand (shared with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check the operand when the instruction is an INLINEASM. This allows memory instructions to be moved around INLINEASM instructions. llvm-svn: 123044
* StrongPHIElimination will never run before TwoAddressInstructionPass.Cameron Zwarich2010-12-191-1/+0
| | | | llvm-svn: 122197
* Remove some checks for StrongPHIElim. These checks make it impossible to use anCameron Zwarich2010-12-191-4/+2
| | | | | | | | | | | alternative register allocator that does not require LiveIntervals by specifying it on the command-line for a target that has StrongPHIElimination enabled by default. These checks are pretty meaningless anyways, since StrongPHIElimination and PHIElimination are never used at the same time. llvm-svn: 122176
* Fix crash compiling a QQQQ REG_SEQUENCE for a Neon vld3_lane operation.Bob Wilson2010-12-171-2/+5
| | | | | | Radar 8776599 llvm-svn: 122018
* Fix a minor bug in two-address pass. It was missing a commute opportunity.Evan Cheng2010-12-141-1/+2
| | | | | | | | | | | | | | | | | | | regB = move RCX regA = op regB, regC RAX = move regA where both regB and regC are killed. If regB is constrainted to non-compatible physical registers but regC is not constrainted at all, then it's better to commute the instruction. movl %edi, %eax shlq $32, %rcx leaq (%rcx,%rax), %rax => movl %edi, %eax shlq $32, %rcx orq %rcx, %rax rdar://8762995 llvm-svn: 121793
* Remove some variables that are never really usedDuncan Sands2010-10-211-1/+0
| | | | | | (gcc-4.6 warns about these). llvm-svn: 117021
* Get rid of static constructors for pass registration. Instead, every pass ↵Owen Anderson2010-10-191-1/+3
| | | | | | | | | | | | | | | | | exposes an initializeMyPassFunction(), which must be called in the pass's constructor. This function uses static dependency declarations to recursively initialize the pass's dependencies. Clients that only create passes through the createFooPass() APIs will require no changes. Clients that want to use the CommandLine options for passes will need to manually call the appropriate initialization functions in PassInitialization.h before parsing commandline arguments. I have tested this with all standard configurations of clang and llvm-gcc on Darwin. It is possible that there are problems with the static dependencies that will only be visible with non-standard options. If you encounter any crash in pass registration/creation, please send the testcase to me directly. llvm-svn: 116820
* Begin adding static dependence information to passes, which will allow us toOwen Anderson2010-10-121-1/+4
| | | | | | | | | perform initialization without static constructors AND without explicit initialization by the client. For the moment, passes are required to initialize both their (potential) dependencies and any passes they preserve. I hope to be able to relax the latter requirement in the future. llvm-svn: 116334
* Now with fewer extraneous semicolons!Owen Anderson2010-10-071-1/+1
| | | | llvm-svn: 115996
* Now that PassInfo and Pass::ID have been separated, move the rest of the ↵Owen Anderson2010-08-231-2/+2
| | | | | | passes over to the new registration API. llvm-svn: 111815
* A REG_SEQUENCE instruction may use the same register twice.Jakob Stoklund Olesen2010-08-091-1/+11
| | | | | | | | | If we are emitting COPY instructions for the REG_SEQUENCE, make sure the kill flag goes on the last COPY. Otherwise we may be using a killed register. <rdar://problem/8287792> llvm-svn: 110589
* Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson2010-08-061-2/+2
| | | | llvm-svn: 110460
* Revert r110396 to fix buildbots.Owen Anderson2010-08-061-2/+2
| | | | llvm-svn: 110410
* Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson2010-08-051-2/+2
| | | | | | | | address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. llvm-svn: 110396
* Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway.Jakob Stoklund Olesen2010-07-161-19/+11
| | | | | | TII::isMoveInstr is going tobe completely removed. llvm-svn: 108507
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