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path: root/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
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* Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.Jakob Stoklund Olesen2011-01-101-1/+1
| | | | | | | | These functions not longer assert when passed 0, but simply return false instead. No functional change intended. llvm-svn: 123155
* Shrink a BitVector that didn't mean to store bits for all physical registers.Jakob Stoklund Olesen2011-01-091-6/+4
| | | | llvm-svn: 123108
* Do not model all INLINEASM instructions as having unmodelled side effects.Evan Cheng2011-01-071-1/+1
| | | | | | | | | | Instead encode llvm IR level property "HasSideEffects" in an operand (shared with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check the operand when the instruction is an INLINEASM. This allows memory instructions to be moved around INLINEASM instructions. llvm-svn: 123044
* StrongPHIElimination will never run before TwoAddressInstructionPass.Cameron Zwarich2010-12-191-1/+0
| | | | llvm-svn: 122197
* Remove some checks for StrongPHIElim. These checks make it impossible to use anCameron Zwarich2010-12-191-4/+2
| | | | | | | | | | | alternative register allocator that does not require LiveIntervals by specifying it on the command-line for a target that has StrongPHIElimination enabled by default. These checks are pretty meaningless anyways, since StrongPHIElimination and PHIElimination are never used at the same time. llvm-svn: 122176
* Fix crash compiling a QQQQ REG_SEQUENCE for a Neon vld3_lane operation.Bob Wilson2010-12-171-2/+5
| | | | | | Radar 8776599 llvm-svn: 122018
* Fix a minor bug in two-address pass. It was missing a commute opportunity.Evan Cheng2010-12-141-1/+2
| | | | | | | | | | | | | | | | | | | regB = move RCX regA = op regB, regC RAX = move regA where both regB and regC are killed. If regB is constrainted to non-compatible physical registers but regC is not constrainted at all, then it's better to commute the instruction. movl %edi, %eax shlq $32, %rcx leaq (%rcx,%rax), %rax => movl %edi, %eax shlq $32, %rcx orq %rcx, %rax rdar://8762995 llvm-svn: 121793
* Remove some variables that are never really usedDuncan Sands2010-10-211-1/+0
| | | | | | (gcc-4.6 warns about these). llvm-svn: 117021
* Get rid of static constructors for pass registration. Instead, every pass ↵Owen Anderson2010-10-191-1/+3
| | | | | | | | | | | | | | | | | exposes an initializeMyPassFunction(), which must be called in the pass's constructor. This function uses static dependency declarations to recursively initialize the pass's dependencies. Clients that only create passes through the createFooPass() APIs will require no changes. Clients that want to use the CommandLine options for passes will need to manually call the appropriate initialization functions in PassInitialization.h before parsing commandline arguments. I have tested this with all standard configurations of clang and llvm-gcc on Darwin. It is possible that there are problems with the static dependencies that will only be visible with non-standard options. If you encounter any crash in pass registration/creation, please send the testcase to me directly. llvm-svn: 116820
* Begin adding static dependence information to passes, which will allow us toOwen Anderson2010-10-121-1/+4
| | | | | | | | | perform initialization without static constructors AND without explicit initialization by the client. For the moment, passes are required to initialize both their (potential) dependencies and any passes they preserve. I hope to be able to relax the latter requirement in the future. llvm-svn: 116334
* Now with fewer extraneous semicolons!Owen Anderson2010-10-071-1/+1
| | | | llvm-svn: 115996
* Now that PassInfo and Pass::ID have been separated, move the rest of the ↵Owen Anderson2010-08-231-2/+2
| | | | | | passes over to the new registration API. llvm-svn: 111815
* A REG_SEQUENCE instruction may use the same register twice.Jakob Stoklund Olesen2010-08-091-1/+11
| | | | | | | | | If we are emitting COPY instructions for the REG_SEQUENCE, make sure the kill flag goes on the last COPY. Otherwise we may be using a killed register. <rdar://problem/8287792> llvm-svn: 110589
* Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson2010-08-061-2/+2
| | | | llvm-svn: 110460
* Revert r110396 to fix buildbots.Owen Anderson2010-08-061-2/+2
| | | | llvm-svn: 110410
* Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson2010-08-051-2/+2
| | | | | | | | address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. llvm-svn: 110396
* Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway.Jakob Stoklund Olesen2010-07-161-19/+11
| | | | | | TII::isMoveInstr is going tobe completely removed. llvm-svn: 108507
* Replace copyRegToReg with COPY everywhere in lib/CodeGen except for FastISel.Jakob Stoklund Olesen2010-07-101-20/+12
| | | | llvm-svn: 108062
* Only collect subreg extracting copies for later coalescing.Jakob Stoklund Olesen2010-07-101-1/+1
| | | | | | This also avoids fatal copies from physregs. llvm-svn: 108061
* Emit COPY instructions instead of using copyRegToReg in InstrEmitter,Jakob Stoklund Olesen2010-07-101-4/+2
| | | | | | | | | ScheduleDAGEmit, TwoAddressLowering, and PHIElimination. This switches the bulk of register copies to using COPY, but many less used copyRegToReg calls remain. llvm-svn: 108050
* Convert EXTRACT_SUBREG to COPY when emitting machine instrs.Jakob Stoklund Olesen2010-07-081-15/+11
| | | | | | | | | EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead. Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg(). The isMoveInstr hook will be removed later. llvm-svn: 107879
* Remove references to INSERT_SUBREG after de-SSA.Jakob Stoklund Olesen2010-07-081-19/+5
| | | | | | | Fix X86InstrInfo::convertToThreeAddressWithLEA to generate COPY instead of INSERT_SUBREG. llvm-svn: 107878
* Revert "Remove references to INSERT_SUBREG after de-SSA" r107725.Jakob Stoklund Olesen2010-07-071-5/+19
| | | | | | Buildbot breakage. llvm-svn: 107744
* Remove references to INSERT_SUBREG after de-SSAJakob Stoklund Olesen2010-07-061-19/+5
| | | | llvm-svn: 107732
* Convert INSERT_SUBREG to COPY in TwoAddressInstructionPass.Jakob Stoklund Olesen2010-07-061-0/+13
| | | | | | | | | INSERT_SUBREG will now only appear in SSA machine instructions. Fix the handling of partial redefs in ProcessImplicitDefs. This is now relevant since partial redef COPY instructions appear. llvm-svn: 107726
* Detect and handle COPY in many places.Jakob Stoklund Olesen2010-07-031-1/+1
| | | | | | | This code is transitional, it will soon be possible to eliminate isExtractSubreg, isInsertSubreg, and isMoveInstr in most places. llvm-svn: 107547
* - Two-address pass should not assume unfolding is always successful.Evan Cheng2010-07-021-8/+6
| | | | | | | | | - X86 unfolding should check if the instructions being unfolded has memoperands. If there is no memoperands, then it must assume conservative alignment. If this would introduce an expensive sse unaligned load / store, then unfoldMemoryOperand etc. should not unfold the instruction. llvm-svn: 107509
* When unfolding a load, avoid assuming which instruction thatDan Gohman2010-06-221-4/+18
| | | | | | kill and dead flags will end up on. llvm-svn: 106520
* Fix the new load-unfolding code to update LiveVariable's dead flags,Dan Gohman2010-06-221-2/+8
| | | | | | in addition to the kill flags. llvm-svn: 106512
* Teach two-address lowering how to unfold a load to open up commutingDan Gohman2010-06-211-0/+84
| | | | | | | | | | | | | | | | | | | opportunities. For example, this lets it emit this: movq (%rax), %rcx addq %rdx, %rcx instead of this: movq %rdx, %rcx addq (%rax), %rcx in the case where %rdx has subsequent uses. It's the same number of instructions, and usually the same encoding size on x86, but it appears faster, and in general, it may allow better scheduling for the load. llvm-svn: 106493
* Only run CoalesceExtSubRegs when we can expect LiveIntervalAnalysis to clean upJakob Stoklund Olesen2010-06-181-2/+5
| | | | | | the inserted INSERT_SUBREGs after us. llvm-svn: 106345
* Add some missing checks for the case where the extract_subregs areBob Wilson2010-06-151-22/+23
| | | | | | | | combined to an insert_subreg, i.e., where the destination register is larger than the source. We need to check that the subregs can be composed for that case in a symmetrical way to the case when the destination is smaller. llvm-svn: 106004
* Generalize the pre-coalescing of extract_subregs feeding reg_sequences,Bob Wilson2010-06-151-33/+83
| | | | | | | | | replacing the overly conservative checks that I had introduced recently to deal with correctness issues. This makes a pretty noticable difference in our testcases where reg_sequences are used. I've updated one test to check that we no longer emit the unnecessary subreg moves. llvm-svn: 105991
* Allow target to place 2-address pass inserted copies in better spots. Thumb2 ↵Evan Cheng2010-06-091-1/+6
| | | | | | will use this to try to avoid breaking up IT blocks. llvm-svn: 105745
* Fix a mistake in my previous change r105437: don't access operand 2 and assumeBob Wilson2010-06-071-3/+2
| | | | | | | that it is an immediate before checking that the instruction is an EXTRACT_SUBREG. llvm-svn: 105585
* Add some missing checks in TwoAddressInstructionPass::CoalesceExtSubRegs.Bob Wilson2010-06-031-4/+21
| | | | | | | | | | | Check that all the instructions are in the same basic block, that the EXTRACT_SUBREGs write to the same subregs that are being extracted, and that the source and destination registers are in the same regclass. Some of these constraints can be relaxed with a bit more work. Jakob suggested that the loop that checks for subregs when NewSubIdx != 0 should use the "nodbg" iterator, so I made that change here, too. llvm-svn: 105437
* Slightly change the meaning of the reMaterialize target hook when the originalJakob Stoklund Olesen2010-06-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | instruction defines subregisters. Any existing subreg indices on the original instruction are preserved or composed with the new subreg index. Also substitute multiple operands mentioning the original register by using the new MachineInstr::substituteRegister() function. This is necessary because there will soon be <imp-def> operands added to non read-modify-write partial definitions. This instruction: %reg1234:foo = FLAP %reg1234<imp-def> will reMaterialize(%reg3333, bar) like this: %reg3333:bar-foo = FLAP %reg333:bar<imp-def> Finally, replace the TargetRegisterInfo pointer argument with a reference to indicate that it cannot be NULL. llvm-svn: 105358
* Rename canCombinedSubRegIndex method to something more grammatically correctBob Wilson2010-06-021-2/+2
| | | | | | and tidy up the comment describing it. llvm-svn: 105339
* Fix an obvious mistake: don't change the operands until all of them have beenBob Wilson2010-06-021-2/+0
| | | | | | checked and it is safe to proceed with the changes. llvm-svn: 105304
* Handle composed subreg indices when processing REQ_SEQUENCE instructions.Jakob Stoklund Olesen2010-05-291-5/+4
| | | | llvm-svn: 105066
* - Change MachineInstr::findRegisterDefOperandIdx so it can also look for defsEvan Cheng2010-05-211-1/+1
| | | | | | | | | | that are aliases of the specified register. - Rename modifiesRegister to definesRegister since it's looking a def of the specific register or one of its super-registers. It's not looking for def of a sub-register or alias that could change the specified register. - Added modifiesRegister to look for defs of aliases. llvm-svn: 104377
* TwoAddressInstructionPass doesn't really know how to merge live intervals whenJakob Stoklund Olesen2010-05-191-1/+6
| | | | | | | | lowering REG_SEQUENCE instructions. Insert copies for REG_SEQUENCE sources not killed to avoid breaking later passes. llvm-svn: 104146
* Fix PR7175. Insert copies of a REG_SEQUENCE source if it is used by other ↵Evan Cheng2010-05-171-1/+15
| | | | | | REG_SEQUENCE instructions. llvm-svn: 103994
* Fix PR7156. If the sources of a REG_SEQUENCE are all IMPLICIT_DEF's. Replace ↵Evan Cheng2010-05-171-2/+11
| | | | | | it with an IMPLICIT_DEF rather than deleting it or else it would be left without a def. llvm-svn: 103984
* Careful with reg_sequence coalescing to not to overwrite sub-register indices.Evan Cheng2010-05-171-40/+77
| | | | llvm-svn: 103971
* Teach two-address pass to do some coalescing while eliminating REG_SEQUENCEEvan Cheng2010-05-141-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | instructions. e.g. %reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0 %reg1027<def> = EXTRACT_SUBREG %reg1026, 6 %reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5 ... %reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12 After REG_SEQUENCE is eliminated, we are left with: %reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0 %reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6 %reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5 The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger sub-register (or combined to be reg1026 itself as is the case here). If it is possible, it will be able to replace references of reg1026 with reg1029 + the larger sub-register index. llvm-svn: 103835
* If REG_SEQUENCE source is livein, copy it first. Also, update livevariables ↵Evan Cheng2010-05-131-4/+23
| | | | | | information when a copy is introduced. llvm-svn: 103680
* Code clean up.Evan Cheng2010-05-121-1/+2
| | | | llvm-svn: 103538
* Ensure REG_SEQUENCE source operands are unique.Evan Cheng2010-05-111-0/+19
| | | | llvm-svn: 103449
* Clear RegSequences vector after eliminating REG_SEQUENCE instructions.Evan Cheng2010-05-101-0/+1
| | | | llvm-svn: 103435
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