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path: root/llvm/lib/CodeGen/TargetSchedule.cpp
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* MI-Sched cleanup. If an instruction has no valid sched class, do not attempt ↵Andrew Trick2013-04-131-0/+2
| | | | | | to check for a variant. llvm-svn: 179451
* Change the default latency for implicit defs.Andrew Trick2013-03-161-1/+4
| | | | | | | | | | | | | | | | Implicit defs are not currently positional and not modeled by the per-operand machine model. Unfortunately, we treat defs that are part of the architectural instruction description, like flags, the same as other implicit defs. Really, they should have a fixed MachineInstr layout and probably shouldn't be "implicit" at all. For now, we'll change the default latency to be the max operand latency. That will give flag setting operands full latency for x86 folded loads. Other kinds of "fake" implicit defs don't occur prior to regalloc anyway, and we would like them to go away postRegAlloc as well. llvm-svn: 177227
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-2/+2
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* misched: TargetSchedule interface for machine resources.Andrew Trick2012-11-061-4/+35
| | | | | | | | | | | Expose the processor resources defined by the machine model to the scheduler and other clients through the TargetSchedule interface. Normalize each resource count with respect to other kinds of resources. This allows scheduling heuristics to balance resources against other kinds of resources and latency. llvm-svn: 167444
* misched: Better handling of invalid latencies in the machine modelAndrew Trick2012-10-171-2/+10
| | | | llvm-svn: 166107
* misched: Handle "transient" non-instructions.Andrew Trick2012-10-111-17/+23
| | | | llvm-svn: 165701
* misched: fall-back to a target hook for instr bundles.Andrew Trick2012-10-101-3/+4
| | | | llvm-svn: 165606
* misched: Use the TargetSchedModel interface wherever possible.Andrew Trick2012-10-101-0/+49
| | | | | | | | Allows the new machine model to be used for NumMicroOps and OutputLatency. Allows the HazardRecognizer to be disabled along with itineraries. llvm-svn: 165603
* misched: Add computeInstrLatency to TargetSchedModel.Andrew Trick2012-10-091-0/+24
| | | | llvm-svn: 165566
* misched: Allow flags to disable hasInstrSchedModel/hasInstrItineraries for ↵Andrew Trick2012-10-091-6/+12
| | | | | | external users of TargetSchedule. llvm-svn: 165564
* Enable -schedmodel, but prefer itineraries until we have more benchmark data.Andrew Trick2012-10-041-52/+51
| | | | llvm-svn: 165188
* TargetSchedule: cleanup computeOperandLatency logic & diagnostics.Andrew Trick2012-09-181-6/+16
| | | | llvm-svn: 164154
* TargetSchedModel API. Implement latency lookup, disabled.Andrew Trick2012-09-181-0/+140
| | | | llvm-svn: 164098
* Revert r164061-r164067. Most of the new subtarget emitter.Andrew Trick2012-09-171-140/+0
| | | | | | | I have to work out the Target/CodeGen header dependencies before putting this back. llvm-svn: 164072
* TargetSchedModel API. Implement latency lookup, disabled.Andrew Trick2012-09-171-0/+140
| | | | llvm-svn: 164065
* TargetSchedModel interface. To be implemented...Andrew Trick2012-09-141-0/+32
llvm-svn: 163934
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