bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Collapse)	Author	Age	Files	Lines
*	misched: Better handling of invalid latencies in the machine model	Andrew Trick	2012-10-17	1	-2/+10
\| \| \| \|	llvm-svn: 166107
*	misched: Handle "transient" non-instructions.	Andrew Trick	2012-10-11	1	-17/+23
\| \| \| \|	llvm-svn: 165701
*	misched: fall-back to a target hook for instr bundles.	Andrew Trick	2012-10-10	1	-3/+4
\| \| \| \|	llvm-svn: 165606
*	misched: Use the TargetSchedModel interface wherever possible.	Andrew Trick	2012-10-10	1	-0/+49
\| \| \| \| \| \| \| \|	Allows the new machine model to be used for NumMicroOps and OutputLatency. Allows the HazardRecognizer to be disabled along with itineraries. llvm-svn: 165603
*	misched: Add computeInstrLatency to TargetSchedModel.	Andrew Trick	2012-10-09	1	-0/+24
\| \| \| \|	llvm-svn: 165566
*	misched: Allow flags to disable hasInstrSchedModel/hasInstrItineraries for ↵	Andrew Trick	2012-10-09	1	-6/+12
\| \| \| \| \| \|	external users of TargetSchedule. llvm-svn: 165564
*	Enable -schedmodel, but prefer itineraries until we have more benchmark data.	Andrew Trick	2012-10-04	1	-52/+51
\| \| \| \|	llvm-svn: 165188
*	TargetSchedule: cleanup computeOperandLatency logic & diagnostics.	Andrew Trick	2012-09-18	1	-6/+16
\| \| \| \|	llvm-svn: 164154
*	TargetSchedModel API. Implement latency lookup, disabled.	Andrew Trick	2012-09-18	1	-0/+140
\| \| \| \|	llvm-svn: 164098
*	Revert r164061-r164067. Most of the new subtarget emitter.	Andrew Trick	2012-09-17	1	-140/+0
\| \| \| \| \| \| \|	I have to work out the Target/CodeGen header dependencies before putting this back. llvm-svn: 164072
*	TargetSchedModel API. Implement latency lookup, disabled.	Andrew Trick	2012-09-17	1	-0/+140
\| \| \| \|	llvm-svn: 164065
*	TargetSchedModel interface. To be implemented...	Andrew Trick	2012-09-14	1	-0/+32
	llvm-svn: 163934