summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
Commit message (Collapse)AuthorAgeFilesLines
* Move the guts of TargetInstrInfoImpl into the TargetInstrInfo class.Jakob Stoklund Olesen2012-11-281-682/+0
| | | | | | | The *Impl class no longer serves a purpose now that the super-class implementation is in CodeGen. llvm-svn: 168759
* Broaden isSchedulingBoundary to check aliases of SP.Andrew Trick2012-11-171-1/+2
| | | | | | | | On PPC the stack pointer is X1, but ADJCALLSTACK writes R1. Fixes PR14315: Register regmask dependency problem with misched. llvm-svn: 168248
* misched: Handle "transient" non-instructions.Andrew Trick2012-10-111-0/+2
| | | | llvm-svn: 165701
* TargetSchedModel API. Implement latency lookup, disabled.Andrew Trick2012-09-181-7/+7
| | | | llvm-svn: 164098
* Revert r164061-r164067. Most of the new subtarget emitter.Andrew Trick2012-09-171-7/+7
| | | | | | | I have to work out the Target/CodeGen header dependencies before putting this back. llvm-svn: 164072
* TargetSchedModel API. Implement latency lookup, disabled.Andrew Trick2012-09-171-7/+7
| | | | llvm-svn: 164065
* Use CloneMachineInstr to make a new MI in commuteInstruction to make the ↵Craig Topper2012-08-311-10/+1
| | | | | | code tolerant of instructions with more than two input operands. llvm-svn: 163000
* Simplify the computeOperandLatency API.Andrew Trick2012-08-231-77/+16
| | | | | | | | | The logic for recomputing latency based on a ScheduleDAG edge was shady. This bypasses the problem by requiring the client to provide operand indices. This ensures consistent use of the machine model's API. llvm-svn: 162420
* Minor cleanup of defaultDefLatency APIAndrew Trick2012-08-081-6/+8
| | | | llvm-svn: 161470
* indentationAndrew Trick2012-07-091-1/+1
| | | | llvm-svn: 159958
* I'm introducing a new machine model to simultaneously allow simpleAndrew Trick2012-07-071-3/+3
| | | | | | | | | | | | | | | | | | | | | | | subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
* Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick2012-07-021-2/+2
| | | | | | Reapplies r159406 with minor cleanup. The regressions appear to have been spurious. llvm-svn: 159541
* Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick2012-06-291-2/+2
| | | | | | This reverts commit r159406. I noticed a performance regression so I'll back out for now. llvm-svn: 159411
* Make NumMicroOps a variable in the subtarget's instruction itinerary.Andrew Trick2012-06-291-2/+2
| | | | | | | | | | | | | | The TargetInstrInfo::getNumMicroOps API does not change, but soon it will be used by MachineScheduler. Now each subtarget can specify the number of micro-ops per itinerary class. For ARM, this is currently always dynamic (-1), because it is used for load/store multiple which depends on the number of register operands. Zero is now a valid number of micro-ops. This can be used for nop pseudo-instructions or instructions that the hardware can squash during dispatch. llvm-svn: 159406
* TargetInstrInfo hooks implemented in codegen should be declared pure virtual.Andrew Trick2012-06-081-13/+13
| | | | llvm-svn: 158233
* Fix Target->Codegen dependence.Andrew Trick2012-06-081-0/+200
| | | | | | | | | | | | | | | | | Bulk move of TargetInstrInfo implementation into TargetInstrInfoImpl. This is dirty because the code isn't part of TargetInstrInfoImpl class, nor should it be, because the methods are not target hooks. However, it's the current mechanism for keeping libTarget useful outside the backend. You'll get a not-so-nice link error if you invoke a TargetInstrInfo method that depends on CodeGen. The TargetInstrInfoImpl class should probably be removed since it doesn't really solve this problem. To really fix this, we probably need separate interfaces for the CodeGen/nonCodeGen sides of TargetInstrInfo. llvm-svn: 158212
* misched: Added ScoreboardHazardRecognizer.Andrew Trick2012-05-241-0/+8
| | | | | | | | | | | | | | | | | | | The Hazard checker implements in-order contraints, or interlocked resources. Ready instructions with hazards do not enter the available queue and are not visible to other heuristics. The major code change is the addition of SchedBoundary to encapsulate the state at the top or bottom of the schedule, including both a pending and available queue. The scheduler now counts cycles in sync with the hazard checker. These are minimum cycle counts based on known hazards. Targets with no itinerary (x86_64) currently remain at cycle 0. To fix this, we need to provide some maximum issue width for all targets. We also need to add the concept of expected latency vs. minimum latency. llvm-svn: 157427
* Fixed commuteInstructions bug where if its called pre-regalloc the subreg ↵Pete Cooper2012-03-281-6/+15
| | | | | | indices weren't commuted llvm-svn: 153579
* Extract method for detecting constant unallocatable physregs.Jakob Stoklund Olesen2012-01-161-13/+1
| | | | | | It is safe to move uses of such registers. llvm-svn: 148259
* Attempt to fix PR11607 by shuffling around which class defines which methods.Eli Friedman2011-12-191-5/+5
| | | | llvm-svn: 146897
* Move parts of lib/Target that use CodeGen into lib/CodeGen.Nick Lewycky2011-12-151-0/+30
| | | | llvm-svn: 146702
* - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a functionEvan Cheng2011-12-141-2/+2
| | | | | | | | | | to finalize MI bundles (i.e. add BUNDLE instruction and computing register def and use lists of the BUNDLE instruction) and a pass to unpack bundles. - Teach more of MachineBasic and MachineInstr methods to be bundle aware. - Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to prevent IT blocks from being broken apart. llvm-svn: 146542
* Move isUnpredicatedTerminator() default implementation to ↵Evan Cheng2011-12-091-0/+13
| | | | | | TargetInstrInfoImpl to break Target's dependency on CodeGen. llvm-svn: 146247
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-10/+15
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* Make use of MachinePointerInfo::getFixedStack.Jay Foad2011-11-151-2/+1
| | | | llvm-svn: 144635
* Permit remat of partial register defs when it is safe.Jakob Stoklund Olesen2011-09-011-5/+10
| | | | | | | | | | | | | | | | | An instruction may define part of a register where the other bits are undefined. In that case, it is safe to rematerialize the instruction. For example: %vreg2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg, %vreg2<imp-def> The extra <imp-def> operand indicates that the instruction does not read the other parts of the virtual register, so a remat is safe. This patch simply allows multiple def operands for the virtual register. It is MI->readsVirtualRegister() that determines if we depend on a previous value so remat is impossible. llvm-svn: 138953
* Prevent remat of partial register redefinitions.Jakob Stoklund Olesen2011-09-011-0/+9
| | | | | | | | | | | | | An instruction that redefines only part of a larger register can never be rematerialized since the virtual register value depends on the old value in other parts of the register. This was fixed for the inline spiller in r138794. This patch fixes the problem for all register allocators, and includes a small test case. <rdar://problem/10032939> llvm-svn: 138944
* Follow up to Jim's r138278. This fixes commuteInstruction so it handles ↵Evan Cheng2011-08-221-10/+12
| | | | | | two-address instructions correctly. I'll let Jim add a test case. :-) llvm-svn: 138289
* Hoist hasLoadFromStackSlot and hasStoreToStackSlot.Jakob Stoklund Olesen2011-08-081-0/+36
| | | | | | | These the methods are target-independent since they simply scan the memory operands. They can live in TargetInstrInfoImpl. llvm-svn: 137063
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-12/+12
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Use TRI::has{Sub,Super}ClassEq() where possible.Jakob Stoklund Olesen2011-06-021-2/+1
| | | | | | No functional change. llvm-svn: 132455
* Permit remat when a virtual register has multiple defs.Jakob Stoklund Olesen2011-04-201-5/+0
| | | | | | | | TII::isTriviallyReMaterializable() shouldn't depend on any properties of the register being defined by the instruction. Rematerialization is going to create a new virtual register anyway. llvm-svn: 129882
* Convert -enable-sched-cycles and -enable-sched-hazard to -disableAndrew Trick2011-01-211-1/+12
| | | | | | | | | | | flags. They are still not enable in this revision. Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with the scheduler's model of operand latency in the selection DAG. Generalized unit tests to work with sched-cycles. llvm-svn: 123969
* Sorry, several patches in one.Evan Cheng2011-01-201-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | TargetInstrInfo: Change produceSameValue() to take MachineRegisterInfo as an optional argument. When in SSA form, targets can use it to make more aggressive equality analysis. Machine LICM: 1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead. 2. Fix a bug which prevent CSE of instructions which are not re-materializable. 3. Use improved form of produceSameValue. ARM: 1. Teach ARM produceSameValue to look pass some PIC labels. 2. Look for operands from different loads of different constant pool entries which have same values. 3. Re-implement PIC GA materialization using movw + movt. Combine the pair with a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible to re-materialize the instruction, allow machine LICM to hoist the set of instructions out of the loop and make it possible to CSE them. It's a bit hacky, but it significantly improve code quality. 4. Some minor bug fixes as well. With the fixes, using movw + movt to materialize GAs significantly outperform the load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap and 176.gcc ~10%. llvm-svn: 123905
* Do not model all INLINEASM instructions as having unmodelled side effects.Evan Cheng2011-01-071-2/+7
| | | | | | | | | | Instead encode llvm IR level property "HasSideEffects" in an operand (shared with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check the operand when the instruction is an INLINEASM. This allows memory instructions to be moved around INLINEASM instructions. llvm-svn: 123044
* Various bits of framework needed for precise machine-level selectionAndrew Trick2010-12-241-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | DAG scheduling during isel. Most new functionality is currently guarded by -enable-sched-cycles and -enable-sched-hazard. Added InstrItineraryData::IssueWidth field, currently derived from ARM itineraries, but could be initialized differently on other targets. Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is active, and if so how many cycles of state it holds. Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry into the scheduler's available queue. ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to get information about it's SUnits, provides RecedeCycle for bottom-up scheduling, correctly computes scoreboard depth, tracks IssueCount, and considers potential stall cycles when checking for hazards. ScheduleDAGRRList now models machine cycles and hazards (under flags). It tracks MinAvailableCycle, drives the hazard recognizer and priority queue's ready filter, manages a new PendingQueue, properly accounts for stall cycles, etc. llvm-svn: 122541
* Generalize PostRAHazardRecognizer so it can be used in any pass forAndrew Trick2010-12-081-3/+3
| | | | | | | | both forward and backward scheduling. Rename it to ScoreboardHazardRecognizer (Scoreboard is one word). Remove integer division from the scoreboard's critical path. llvm-svn: 121274
* force clients of MachineFunction::getMachineMemOperand to provide aChris Lattner2010-09-211-3/+3
| | | | | | | MachinePointerInfo, propagating the type out a level of API. Remove the old MachineFunction::getMachineMemOperand impl. llvm-svn: 114393
* Teach if-converter to be more careful with predicating instructions that wouldEvan Cheng2010-09-101-1/+1
| | | | | | | | | | | take multiple cycles to decode. For the current if-converter clients (actually only ARM), the instructions that are predicated on false are not nops. They would still take machine cycles to decode. Micro-coded instructions such as LDM / STM can potentially take multiple cycles to decode. If-converter should take treat them as non-micro-coded simple instructions. llvm-svn: 113570
* remove the JIT "NeedsExactSize" feature and supporting logic.Chris Lattner2010-07-221-13/+0
| | | | llvm-svn: 109167
* Don't add memory operands to storeRegToStackSlot / loadRegFromStackSlot results,Jakob Stoklund Olesen2010-07-131-38/+32
| | | | | | | | | | | they already have one. This fixes the himenobmtxpa miscompilation on ARM. The PostRA scheduler got confused by the double memoperand and hoisted a stack slot load above a store to the same slot. llvm-svn: 108219
* Remove TargetInstrInfo::copyRegToReg entirely.Jakob Stoklund Olesen2010-07-111-17/+0
| | | | | | | Targets must now implement TargetInstrInfo::copyPhysReg instead. There is no longer a default implementation forwarding to copyRegToReg. llvm-svn: 108095
* Automatically fold COPY instructions into stack load/store.Jakob Stoklund Olesen2010-07-091-9/+75
| | | | llvm-svn: 108012
* Change TII::foldMemoryOperand API to require the machine instruction to beJakob Stoklund Olesen2010-07-091-4/+11
| | | | | | | | | | | | | | inserted in a MBB, and return an already inserted MI. This target API change is necessary to allow foldMemoryOperand to call storeToStackSlot and loadFromStackSlot when folding a COPY to a stack slot reference in a target independent way. The foldMemoryOperandImpl hook is going to change in the same way, but I'll wait until COPY folding is actually implemented. Most targets only fold copies and won't need to specialize this hook at all. llvm-svn: 107991
* Add TargetInstrInfo::copyPhysReg hook and use it from LowerSubregs.Jakob Stoklund Olesen2010-07-081-0/+17
| | | | | | | | | This target hook is intended to replace copyRegToReg entirely, but for now it calls copyRegToReg. Any remaining calls to copyRegToReg wil be replaced by COPY instructions. llvm-svn: 107854
* Tail merging pass shall not break up IT blocks. rdar://8115404Evan Cheng2010-06-221-0/+2
| | | | llvm-svn: 106517
* Allow ARM if-converter to be run after post allocation scheduling.Evan Cheng2010-06-181-0/+42
| | | | | | | | | | | | | | | | - This fixed a number of bugs in if-converter, tail merging, and post-allocation scheduler. If-converter now runs branch folding / tail merging first to maximize if-conversion opportunities. - Also changed the t2IT instruction slightly. It now defines the ITSTATE register which is read by instructions in the IT block. - Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't change the instruction ordering in the IT block (since IT mask has been finalized). It also ensures no other instructions can be scheduled between instructions in the IT block. This is not yet enabled. llvm-svn: 106344
* - Do away with SimpleHazardRecognizer.h. It's not used and offers little value.Evan Cheng2010-06-141-0/+7
| | | | | | - Rename ExactHazardRecognizer to PostRAHazardRecognizer and move its header to include to allow targets to extend it. llvm-svn: 105959
* Code formatting.Evan Cheng2010-06-121-5/+3
| | | | llvm-svn: 105861
* Slightly change the meaning of the reMaterialize target hook when the originalJakob Stoklund Olesen2010-06-021-10/+2
| | | | | | | | | | | | | | | | | | | | | | | instruction defines subregisters. Any existing subreg indices on the original instruction are preserved or composed with the new subreg index. Also substitute multiple operands mentioning the original register by using the new MachineInstr::substituteRegister() function. This is necessary because there will soon be <imp-def> operands added to non read-modify-write partial definitions. This instruction: %reg1234:foo = FLAP %reg1234<imp-def> will reMaterialize(%reg3333, bar) like this: %reg3333:bar-foo = FLAP %reg333:bar<imp-def> Finally, replace the TargetRegisterInfo pointer argument with a reference to indicate that it cannot be NULL. llvm-svn: 105358
OpenPOWER on IntegriCloud