| Commit message (Collapse) | Author | Age | Files | Lines |
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llvm-svn: 76356
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llvm-svn: 75440
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llvm-svn: 73750
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llvm-svn: 73634
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trivial rewriter.
llvm-svn: 72729
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llvm-svn: 72114
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llvm-svn: 72113
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llvm-svn: 72112
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llvm-svn: 72030
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llvm-svn: 71057
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This fixes a very subtle bug. vr defined by an implicit_def is allowed overlap with any register since it doesn't actually modify anything. However, if it's used as a two-address use, its live range can be extended and it can be spilled. The spiller must take care not to emit a reload for the vn number that's defined by the implicit_def. This is both a correctness and performance issue.
llvm-svn: 69743
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register is available and when it's profitable.
e.g.
xorq %r12<kill>, %r13
addq %rax, -184(%rbp)
addq %r13, -184(%rbp)
==>
xorq %r12<kill>, %r13
movq -184(%rbp), %r12
addq %rax, %r12
addq %r13, %r12
movq %r12, -184(%rbp)
Two more instructions, but fewer memory accesses. It can also open up
opportunities for more optimizations.
llvm-svn: 69341
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llvm-svn: 68099
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llvm-svn: 68092
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the would be loaded value is available in a register. It needs to check if it's legal to clobber the register. Also, the register can contain values of multiple spill slots, make sure to check all instead of just the one being unfolded.
llvm-svn: 67068
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llvm-svn: 66780
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No (intended) functionality change.
llvm-svn: 66720
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