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path: root/llvm/lib/CodeGen/SimpleRegisterCoalescing.h
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* Stop the iterator in ValueLiveAt from potentially running off the end of the ↵Lang Hames2009-10-301-1/+2
| | | | | | interval. llvm-svn: 85599
* Reapply r85338.Bill Wendling2009-10-291-0/+5
| | | | llvm-svn: 85514
* Reverting r85338 for now. It's causing a bootstrap failure on PPC darwin9.Bill Wendling2009-10-291-5/+0
| | | | | | | | --- Reverse-merging r85338 into '.': U lib/CodeGen/SimpleRegisterCoalescing.cpp U lib/CodeGen/SimpleRegisterCoalescing.h llvm-svn: 85454
* Fixed a bug in the coalescer where intervals were occasionally merged ↵Lang Hames2009-10-271-0/+5
| | | | | | despite a real interference. This fixes rdar://problem/7157961. llvm-svn: 85338
* Factor out LiveIntervalAnalysis' code to determine whether an instructionDan Gohman2009-10-091-0/+1
| | | | | | | | | | | | | | is trivially rematerializable and integrate it into TargetInstrInfo::isTriviallyReMaterializable. This way, all places that need to know whether an instruction is rematerializable will get the same answer. This enables the useful parts of the aggressive-remat option by default -- using AliasAnalysis to determine whether a memory location is invariant, and removes the questionable parts -- rematting operations with virtual register inputs that may not be live everywhere. llvm-svn: 83687
* Renamed MachineInstrIndex to LiveIndex.Lang Hames2009-10-031-4/+4
| | | | llvm-svn: 83254
* Clean up spill weight computation. Also some changes to give loop inductionEvan Cheng2009-09-211-6/+7
| | | | | | | | | | variable increment / decrement slighter high priority. This has major impact on some micro-benchmarks. On MultiSource/Applications and spec tests, it's a minor win. It also reduce 256.bzip instruction count by 8%, 55 on 164.gzip on i386 / Darwin. llvm-svn: 82485
* Remove -new-coalescer-heuristic. It's not useful.Evan Cheng2009-09-121-56/+2
| | | | llvm-svn: 81600
* Replaces uses of unsigned for indexes in LiveInterval and VNInfo withLang Hames2009-09-041-3/+6
| | | | | | | | a new class, MachineInstrIndex, which hides arithmetic details from most clients. This is a step towards allowing the register allocator to update/insert code during allocation. llvm-svn: 81040
* Change Pass::print to take a raw ostream instead of std::ostream,Chris Lattner2009-08-231-4/+1
| | | | | | update all code that this affects. llvm-svn: 79830
* Simplify some more.Evan Cheng2009-07-171-6/+0
| | | | llvm-svn: 76239
* Simplify the coalescer (finally!) by making ↵Evan Cheng2009-07-171-4/+0
| | | | | | LiveIntervals::processImplicitDefs a little more aggressive and teaching liveintervals to make use of isUndef marker on MachineOperands. llvm-svn: 76223
* Let callers decide the sub-register index on the def operand of ↵Evan Cheng2009-07-161-1/+1
| | | | | | | | rematerialized instructions. Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right. llvm-svn: 75900
* Rename RemoveCopiesFromValNo to TurnCopiesFromValNoToImpDefs.Evan Cheng2009-06-161-4/+4
| | | | llvm-svn: 73479
* Update to in-place spilling framework. Includes live interval scaling and ↵Lang Hames2009-06-021-1/+1
| | | | | | trivial rewriter. llvm-svn: 72729
* Add a smarter heuristic to determine when to coalesce a virtual register ↵Evan Cheng2009-04-301-0/+12
| | | | | | | | with a physical one. More specifically, it avoid tying a virtual register in the loop with a physical register defined / used outside the loop. When it determines it's not profitable, it will use the physical register as the allocation preference instead. This is *not* turned on by default. Testing indicates this is just as likely to pessimize code. The main issue seems to be allocation preference doesn't work effectively. That will change once I've taught register allocator "swapping". llvm-svn: 70503
* ReMaterializeTrivialDef need to trim the live interval to the last kill if ↵Evan Cheng2009-02-051-0/+9
| | | | | | the copy kills the source register. This fixes uint64tof64.ll after ARM::MOVi is marked as isAsCheapAsAMove. llvm-svn: 63853
* Cross register class coalescing. Not yet enabled.Evan Cheng2009-01-231-15/+8
| | | | llvm-svn: 62832
* Refactor code. No functionality change.Evan Cheng2009-01-201-0/+14
| | | | llvm-svn: 62573
* Tidy up #includes, deleting a bunch of unnecessary #includes.Dan Gohman2009-01-051-2/+0
| | | | llvm-svn: 61715
* Remove val# defined by a remat'ed def that is now dead.Evan Cheng2008-10-271-0/+5
| | | | llvm-svn: 58294
* Re-materalized definition instructions may be dead. Whack them.Evan Cheng2008-09-191-0/+4
| | | | llvm-svn: 56352
* Fix PR2748. Avoid coalescing physical register with virtual register which ↵Evan Cheng2008-09-111-0/+7
| | | | | | | | | | | would create illegal extract_subreg. e.g. vr1024 = extract_subreg vr1025, 1 ... vr1024 = mov8rr AH If vr1024 is coalesced with AH, the extract_subreg is now illegal since AH does not have a super-reg whose sub-register 1 is AH. llvm-svn: 56118
* Tidy up several unbeseeming casts from pointer to intptr_t.Dan Gohman2008-09-041-1/+1
| | | | llvm-svn: 55779
* Re-apply 55467 with fix. If copy is being replaced by remat'ed def, transfer ↵Evan Cheng2008-08-301-0/+7
| | | | | | the implicit defs onto the remat'ed instruction. llvm-svn: 55564
* Revert r55467; it causes regressions in UnitTests/Vector/divides,Dan Gohman2008-08-281-7/+0
| | | | | | Benchmarks/sim/sim, and others on x86-64. llvm-svn: 55475
* If a copy isn't coalesced, but its src is defined by trivial computation. ↵Evan Cheng2008-08-281-0/+7
| | | | | | Re-materialize the src to replace the copy. llvm-svn: 55467
* Fix a compile-time regression introduced by my heuristic-changing patch. I ↵Owen Anderson2008-07-231-1/+2
| | | | | | | | | forgot to multiply the instruction count by a constant factor in a few places, which caused the register allocator to require many more iterations. llvm-svn: 53959
* Change the heuristics used in the coalescer, register allocator, and withinOwen Anderson2008-07-221-1/+1
| | | | | | | live intervals itself to use an instruction count approximation that is not affected by inserting empty indices. llvm-svn: 53937
* Coalesce copy from one register class to a sub register class. e.g. ↵Evan Cheng2008-06-191-3/+13
| | | | | | X86::MOV16to16_. llvm-svn: 52480
* The coalescer doesn't need LiveVariables now that we have register use ↵Owen Anderson2008-05-301-1/+0
| | | | | | iterators. llvm-svn: 51790
* After reading memory that's already freed.Evan Cheng2008-04-161-4/+4
| | | | llvm-svn: 49810
* Add comment.Evan Cheng2008-04-101-0/+2
| | | | llvm-svn: 49469
* - More aggressively coalescing away copies whose source is defined by an ↵Evan Cheng2008-04-091-2/+20
| | | | | | | | implicit_def. - Added insert_subreg coalescing support. llvm-svn: 49448
* - Turn copies of implicit_def into implicit_def instructions.Evan Cheng2008-04-031-0/+6
| | | | | | - Be smarter about coalescing copies from implicit_def. llvm-svn: 49168
* Rewrite code that propagate isDead information after a dead copy is ↵Evan Cheng2008-03-181-1/+5
| | | | | | coalesced. This remove some ugly spaghetti code and fixed a number of subtle bugs. llvm-svn: 48490
* - Fix a subtle bug in RemoveCopyByCommutingDef. ALR is the live range where ↵Evan Cheng2008-03-101-0/+4
| | | | | | | | | | | | | | | | | | the source is defined; BLR is the live range which is defined by the copy. If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g. A = or A, B ... B = A ... C = A<kill> ... = B then do not add kills of A to the newly created B interval. - Also fix some kill info update bug. llvm-svn: 48141
* Fix a coalescer bug wrt how dead copy interval is shortened.Evan Cheng2008-03-051-0/+6
| | | | llvm-svn: 47966
* Refactor code. Remove duplicated functions that basically do the same thing asEvan Cheng2008-03-051-4/+0
| | | | | | findRegisterUseOperandIdx, findRegisterDefOperandIndx. Fix some naming inconsistencies. llvm-svn: 47927
* No need for coalescer to update kills. Only copies are coalesced and those ↵Evan Cheng2008-02-291-8/+0
| | | | | | instructions will be deleted. Doh. llvm-svn: 47749
* Refactor some code; check if commuteInstruction is able to commute the ↵Evan Cheng2008-02-161-0/+5
| | | | | | instruction. llvm-svn: 47208
* - Removing the infamous r2rMap_ and rep() method. Now the coalescer will updateEvan Cheng2008-02-151-51/+26
| | | | | | | register defs and uses after each successful coalescing. - Also removed a number of hacks and fixed some subtle kill information bugs. llvm-svn: 47167
* Initial support for copy elimination by commuting its definition MI.Evan Cheng2008-02-131-1/+8
| | | | | | | | | | | | | | | | | | | | | PR1877. A3 = op A2 B0<kill> ... B1 = A3 <- this copy ... = op A3 <- more uses ==> B2 = op B0 A2<kill> ... B1 = B2 <- now an identify copy ... = op B2 <- more uses This speeds up FreeBench/neural by 29%, Olden/bh by 12%, oopack_v1p8 by 53%. llvm-svn: 47046
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-101-2/+2
| | | | llvm-svn: 46930
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* Add explicit keywords, and fix a minor typo that they uncovered.Dan Gohman2007-12-141-2/+3
| | | | llvm-svn: 45034
* Switch over to MachineLoopInfo.Evan Cheng2007-12-111-2/+2
| | | | llvm-svn: 44838
* First step towards moving the coalescer to priority_queue based machinery.Evan Cheng2007-11-061-16/+70
| | | | llvm-svn: 43764
* Move SimpleRegisterCoalescing.h to lib/CodeGen since there is now a commonEvan Cheng2007-11-051-0/+184
register coalescer interface: RegisterCoalescing. llvm-svn: 43714
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