| Commit message (Collapse) | Author | Age | Files | Lines |
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for a copy instruction. PR2775.
llvm-svn: 57458
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llvm-svn: 57388
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llvm-svn: 57259
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isReg, etc., from isRegister, etc.
llvm-svn: 57006
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llvm-svn: 56848
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"If a re-materializable instruction has a register
operand, the spiller will change the register operand's
spill weight to HUGE_VAL to avoid it being spilled.
However, if the operand is already in the queue ready
to be spilled, avoid re-materializing it".
llvm-svn: 56837
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change the register operand's spill weight to HUGE_VAL to avoid it being spilled. However, if the operand is already in the queue ready to be spilled, avoid re-materializing it.
llvm-svn: 56835
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RA problem by expanding the live interval of an
earlyclobber def back one slot. Remove
overlap-earlyclobber throughout. Remove
earlyclobber bits and their handling from
live internals.
llvm-svn: 56539
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llvm-svn: 56469
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Check bits for preferred register.
llvm-svn: 56384
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llvm-svn: 56372
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llvm-svn: 56352
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llvm-svn: 56287
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fix 56165 - do not mark val# copy field if the copy does not define the val#.
llvm-svn: 56199
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isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.
llvm-svn: 56189
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of coalescing. e.g.
vr2 = OR vr0, vr1
=>
vr2 = OR vr1, vr1 // after coalescing vr0 with vr1
Update the value# of the destination register with the copy instruction if that happens.
llvm-svn: 56165
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would create illegal extract_subreg. e.g.
vr1024 = extract_subreg vr1025, 1
...
vr1024 = mov8rr AH
If vr1024 is coalesced with AH, the extract_subreg is now illegal since AH does not have a super-reg whose sub-register 1 is AH.
llvm-svn: 56118
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check.
llvm-svn: 56112
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before trying to manipulate it. This
was exposed by fast isel's handling of shifts on X86-64. With this, FreeBench/pcompress2 passes on X86-64 in fast isel.
llvm-svn: 56067
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llvm-svn: 56037
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llvm-svn: 56019
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the implicit defs onto the remat'ed instruction.
llvm-svn: 55564
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Benchmarks/sim/sim, and others on x86-64.
llvm-svn: 55475
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Re-materialize the src to replace the copy.
llvm-svn: 55467
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had to be propoagated down into all the targets and up into all clients of this API.
llvm-svn: 54802
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llvm-svn: 54780
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the r2iMap_ by value. This will prevent references to them from being invalidated
if the map is changed.
llvm-svn: 54763
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llvm-svn: 54347
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has been extended due to coalescing.
llvm-svn: 54346
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forgot
to multiply the instruction count by a constant factor in a few places, which
caused the register allocator to require many more iterations.
llvm-svn: 53959
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live intervals itself to use an instruction count approximation that is
not affected by inserting empty indices.
llvm-svn: 53937
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since it's less precise.
llvm-svn: 53734
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instruction in the block.
llvm-svn: 52649
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llvm-svn: 52572
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X86::MOV16to16_.
llvm-svn: 52480
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that are not affected.
llvm-svn: 52430
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iterators.
llvm-svn: 51790
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llvm-svn: 51648
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BB1:
vr1025 = copy vr1024
..
BB2:
vr1024 = op
= op vr1025
<loop eventually branch back to BB1>
Even though vr1025 is copied from vr1024, it's not safe to coalesced them since live range of vr1025 intersects the def of vr1024. This happens when vr1025 is assigned the value of the previous iteration of vr1024 in the loop.
llvm-svn: 51394
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address of the PassInfo directly instead of calling getPassInfo.
This eliminates a bunch of dynamic initializations of static data.
Also, fold RegisterPassBase into PassInfo, make a bunch of its
data members const, and rearrange some code to initialize data
members in constructors instead of using setter member functions.
llvm-svn: 51022
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several things that were neither in an anonymous namespace nor static
but not intended to be global.
llvm-svn: 51017
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e.g.
vr1024<2> extract_subreg vr1025, 2
If vr1024 do not have the same register class as vr1025, it's not safe to coalesce this away. For example, vr1024 might be a GPR32 while vr1025 might be a GPR64.
llvm-svn: 50385
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removed.
- Do not iterate over SmallPtrSet, the order of iteration is not deterministic.
llvm-svn: 50209
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llvm-svn: 49913
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block branch.
llvm-svn: 49911
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destination operand has already been coalesced with another register that's defined by a insert_subreg or extract_subreg.
llvm-svn: 49843
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llvm-svn: 49841
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llvm-svn: 49832
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llvm-svn: 49810
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llvm-svn: 49807
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