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path: root/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp
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* Update to in-place spilling framework. Includes live interval scaling and ↵Lang Hames2009-06-021-1/+1
| | | | | | trivial rewriter. llvm-svn: 72729
* Fixed PR4090.Lang Hames2009-05-111-1/+16
| | | | llvm-svn: 71495
* Join cross class copies using getCommonSubClass()Jakob Stoklund Olesen2009-04-301-20/+8
| | | | llvm-svn: 70513
* Add a smarter heuristic to determine when to coalesce a virtual register ↵Evan Cheng2009-04-301-20/+161
| | | | | | | | with a physical one. More specifically, it avoid tying a virtual register in the loop with a physical register defined / used outside the loop. When it determines it's not profitable, it will use the physical register as the allocation preference instead. This is *not* turned on by default. Testing indicates this is just as likely to pessimize code. The main issue seems to be allocation preference doesn't work effectively. That will change once I've taught register allocator "swapping". llvm-svn: 70503
* Move getMatchingSuperReg() out of coalescer and into TargetRegisterInfo.Evan Cheng2009-04-281-16/+4
| | | | llvm-svn: 70309
* Don't coalesce a physical register with an incompatible virtual register.Jakob Stoklund Olesen2009-04-281-5/+42
| | | | | | | | | | If the physical register does not belong to the virtual register's regclass, don't coalesce. The physical register could be an invalid operand for an instruction using the vreg. The regclass matching is done after determining the actual subregisters being copied. llvm-svn: 70298
* Don't skip the CopyMI when removing kill markers.Owen Anderson2009-04-271-2/+0
| | | | | | | This should have no effect on generated code, but makes the intermediate state of the coalescer more sane. llvm-svn: 70238
* Update comments.Evan Cheng2009-04-231-2/+2
| | | | llvm-svn: 69919
* Fix an obvious type.Evan Cheng2009-04-231-1/+1
| | | | llvm-svn: 69918
* Implement support for using modeling implicit-zero-extension on x86-64Dan Gohman2009-04-081-24/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG instructions), and teach the DAGCombiner to take advantage of this on targets which support it. This eliminates many redundant zero-extension operations on x86-64. This adds a new TargetLowering hook, isZExtFree. It's similar to isTruncateFree, except it only applies to actual definitions, and not no-op truncates which may not zero the high bits. Also, this adds a new optimization to SimplifyDemandedBits: transform operations like x+y into (zext (add (trunc x), (trunc y))) on targets where all the casts are no-ops. In contexts where the high part of the add is explicitly masked off, this allows the mask operation to be eliminated. Fix the DAGCombiner to avoid undoing these transformations to eliminate casts on targets where the casts are no-ops. Also, this adds a new two-address lowering heuristic. Since two-address lowering runs before coalescing, it helps to be able to look through copies when deciding whether commuting and/or three-address conversion are profitable. Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle the case that a clobber range extended both before and beyond an existing live range. In that case, multiple live ranges need to be added. This was exposed by the new subreg coalescing code. Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the spiller behavior it was looking for no longer occurrs with the new instruction selection. llvm-svn: 68576
* Fix grammar-o in comment.Bill Wendling2009-03-301-1/+1
| | | | llvm-svn: 68057
* My last coalescer fix introduced a subtler one. It's aborting a commuting ↵Evan Cheng2009-03-111-5/+11
| | | | | | optimization too late and left the live intervals to be out of sync with instructions. This fixes 8b10b. llvm-svn: 66715
* Two coalescer fixes in one.Evan Cheng2009-03-111-6/+20
| | | | | | | 1. Use the same value# to represent unknown values being merged into sub-registers. 2. When coalescer commute an instruction and the destination is a physical register, update its sub-registers by merging in the extended ranges. llvm-svn: 66610
* If a use operand is marked isKill, don't forget to add kill to its live ↵Evan Cheng2009-02-221-4/+6
| | | | | | interval as well. llvm-svn: 65279
* Fix another case ShortenDeadCopySrcLiveRange is shortening too much. No test ↵Evan Cheng2009-02-091-6/+13
| | | | | | case possible since I don't know what to grep for. :-( llvm-svn: 64125
* Fix PR3486. Fix a bug in code that manually patch physical register live ↵Evan Cheng2009-02-081-14/+25
| | | | | | interval after its sub-register is coalesced with a virtual register. llvm-svn: 64082
* Strengthen the previous check.Evan Cheng2009-02-081-4/+5
| | | | llvm-svn: 64076
* r64073 commit message is lost. Here it is:Evan Cheng2009-02-081-3/+4
| | | | | | | | | Right now if the coalesced copy def is dead and its src is a kill, and that there are now other uses within the live range, the coalescer would mark the def of the source register as dead. But it should also check if there are other kills which means the value has other uses not in the live range. llvm-svn: 64075
* (no commit message)Evan Cheng2009-02-081-3/+10
| | | | llvm-svn: 64073
* isAsCheapAsMove instructions can have register src operands. Check if they ↵Evan Cheng2009-02-051-0/+3
| | | | | | | | are really re-materializable. This fixes sse.expandfft and sse.stepfft. llvm-svn: 63890
* ReMaterializeTrivialDef need to trim the live interval to the last kill if ↵Evan Cheng2009-02-051-79/+99
| | | | | | the copy kills the source register. This fixes uint64tof64.ll after ARM::MOVi is marked as isAsCheapAsAMove. llvm-svn: 63853
* Skip over zero registers.Evan Cheng2009-02-041-0/+2
| | | | llvm-svn: 63748
* Only check if coalescing is worthwhile when the result is targeting a more ↵Evan Cheng2009-01-231-1/+6
| | | | | | restrictive register class. llvm-svn: 62837
* Cross register class coalescing. Not yet enabled.Evan Cheng2009-01-231-94/+115
| | | | llvm-svn: 62832
* Change TargetInstrInfo::isMoveInstr to return source and destination ↵Evan Cheng2009-01-201-28/+34
| | | | | | sub-register indices as well. llvm-svn: 62600
* Refactor code. No functionality change.Evan Cheng2009-01-201-34/+75
| | | | llvm-svn: 62573
* Use assertions to check for conditions that should never happen.Dan Gohman2009-01-131-12/+6
| | | | llvm-svn: 62178
* Un-tabify.Evan Cheng2009-01-131-1/+1
| | | | llvm-svn: 62151
* FIX llvm-gcc bootstrap on x86_64 linux. If a virtual register is copied to a ↵Evan Cheng2009-01-131-0/+13
| | | | | | physical register, it's not necessarily defined by a copy. We have to watch out it doesn't clobber any sub-register that might be live during its live interval. If the live interval crosses a basic block, then it's not safe to check with the less conservative check (by scanning uses and defs) because it's possible a sub-register might be live out of the block. llvm-svn: 62144
* The coalescer does not coalesce a virtual register to a physical register if ↵Evan Cheng2009-01-071-17/+35
| | | | | | | | | | | | | | any of the physical register's sub-register live intervals overlaps with the virtual register. This is overly conservative. It prevents a extract_subreg from being coalesced away: v1024 = EDI // not killed = = EDI One possible solution is for the coalescer to examine the sub-register live intervals in the same manner as the physical register. Another possibility is to examine defs and uses (when needed) of sub-registers. Both solutions are too expensive. For now, look for "short virtual intervals" and scan instructions to look for conflict instead. This is a small win on x86-64. e.g. It shaves 403.gcc by ~80 instructions. llvm-svn: 61847
* squash warnings.Devang Patel2009-01-051-1/+1
| | | | llvm-svn: 61707
* Fix PR3149. If an early clobber def is a physical register and it is tied to ↵Evan Cheng2008-12-191-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | an input operand, it effectively extends the live range of the physical register. Currently we do not have a good way to represent this. 172 %ECX<def> = MOV32rr %reg1039<kill> 180 INLINEASM <es:subl $5,$1 sbbl $3,$0>, 10, %EAX<def>, 14, %ECX<earlyclobber,def>, 9, %EAX<kill>, 36, <fi#0>, 1, %reg0, 0, 9, %ECX<kill>, 36, <fi#1>, 1, %reg0, 0 188 %EAX<def> = MOV32rr %EAX<kill> 196 %ECX<def> = MOV32rr %ECX<kill> 204 %ECX<def> = MOV32rr %ECX<kill> 212 %EAX<def> = MOV32rr %EAX<kill> 220 %EAX<def> = MOV32rr %EAX 228 %reg1039<def> = MOV32rr %ECX<kill> The early clobber operand ties ECX input to the ECX def. The live interval of ECX is represented as this: %reg20,inf = [46,47:1)[174,230:0) 0@174-(230) 1@46-(47) The right way to represent this is something like %reg20,inf = [46,47:2)[174,182:1)[181:230:0) 0@174-(182) 1@181-230 @2@46-(47) Of course that won't work since that means overlapping live ranges defined by two val#. The workaround for now is to add a bit to val# which says the val# is redefined by a early clobber def somewhere. This prevents the move at 228 from being optimized away by SimpleRegisterCoalescing::AdjustCopiesBackFrom. llvm-svn: 61259
* Perform this loop only when the -debug flag is specified.Bill Wendling2008-12-191-5/+7
| | | | llvm-svn: 61238
* Remove val# defined by a remat'ed def that is now dead.Evan Cheng2008-10-271-2/+25
| | | | llvm-svn: 58294
* When the coalescer is doing rematerializing, have it removeDan Gohman2008-10-211-2/+3
| | | | | | | | | | | | | | | | | | | | the copy instruction from the instruction list before asking the target to create the new instruction. This gets the old instruction out of the way so that it doesn't interfere with the target's rematerialization code. In the case of x86, this helps it find more cases where EFLAGS is not live. Also, in the X86InstrInfo.cpp, teach isSafeToClobberEFLAGS to check to see if it reached the end of the block after scanning each instruction, instead of just before. This lets it notice when the end of the block is only two instructions away, without doing any additional scanning. These changes allow rematerialization to clobber EFLAGS in more cases, for example using xor instead of mov to set the return value to zero in the included testcase. llvm-svn: 57872
* Also update sub-register intervals after a trivial computation is rematt'ed ↵Evan Cheng2008-10-131-0/+10
| | | | | | for a copy instruction. PR2775. llvm-svn: 57458
* fix typoChris Lattner2008-10-111-1/+1
| | | | llvm-svn: 57388
* Add an option to enable StrongPHIElimination, for ease of testing.Owen Anderson2008-10-071-1/+5
| | | | llvm-svn: 57259
* Switch the MachineOperand accessors back to the short names likeDan Gohman2008-10-031-5/+5
| | | | | | isReg, etc., from isRegister, etc. llvm-svn: 57006
* Re-apply 56835 along with header file changes.Evan Cheng2008-09-301-1/+2
| | | | llvm-svn: 56848
* Revert commit 56835 since it breaks the build.Duncan Sands2008-09-301-2/+1
| | | | | | | | | | "If a re-materializable instruction has a register operand, the spiller will change the register operand's spill weight to HUGE_VAL to avoid it being spilled. However, if the operand is already in the queue ready to be spilled, avoid re-materializing it". llvm-svn: 56837
* If a re-materializable instruction has a register operand, the spiller will ↵Evan Cheng2008-09-301-1/+2
| | | | | | change the register operand's spill weight to HUGE_VAL to avoid it being spilled. However, if the operand is already in the queue ready to be spilled, avoid re-materializing it. llvm-svn: 56835
* Next round of earlyclobber handling. Approach theDale Johannesen2008-09-241-12/+0
| | | | | | | | | | RA problem by expanding the live interval of an earlyclobber def back one slot. Remove overlap-earlyclobber throughout. Remove earlyclobber bits and their handling from live internals. llvm-svn: 56539
* Mark several codegen passes as preserving all analysis.Evan Cheng2008-09-221-2/+2
| | | | llvm-svn: 56469
* Teach coalescer about earlyclobber bits.Dale Johannesen2008-09-201-0/+12
| | | | | | Check bits for preferred register. llvm-svn: 56384
* Continue after removing the current MI.Evan Cheng2008-09-191-0/+1
| | | | llvm-svn: 56372
* Re-materalized definition instructions may be dead. Whack them.Evan Cheng2008-09-191-7/+29
| | | | llvm-svn: 56352
* Unallocatable registers do not have live intervals.Evan Cheng2008-09-171-1/+3
| | | | llvm-svn: 56287
* Correctly update kill infos after extending a live range and merge 2 val#'s; ↵Evan Cheng2008-09-151-3/+8
| | | | | | fix 56165 - do not mark val# copy field if the copy does not define the val#. llvm-svn: 56199
* Remove isImm(), isReg(), and friends, in favor of Dan Gohman2008-09-131-2/+2
| | | | | | | | | isImmediate(), isRegister(), and friends, to avoid confusion about having two different names with the same meaning. I'm not attached to the longer names, and would be ok with changing to the shorter names if others prefer it. llvm-svn: 56189
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