summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* Convert DOUT to DEBUG(errs()...).Bill Wendling2009-08-221-59/+95
| | | | llvm-svn: 79765
* Modified VNInfo. The "copy" member is now a union which holds the copy for a ↵Lang Hames2009-08-101-15/+15
| | | | | | register interval, or the defining register for a stack interval. Access is via getCopy/setCopy and getReg/setReg. llvm-svn: 78620
* Another coalescer bug. When a dead copy is eliminated, transfer the kill to ↵Evan Cheng2009-08-071-5/+6
| | | | | | a def of the exact register rather than a super-register. llvm-svn: 78376
* Rename a variable to make MSVC happy.Benjamin Kramer2009-08-051-3/+3
| | | | llvm-svn: 78202
* Another nasty coalescer bug (is there another kind):Evan Cheng2009-08-051-5/+19
| | | | | | | | | | | | | | | | After coalescing reg1027's def and kill are both at the same point: %reg1027,0.000000e+00 = [56,814:0) 0@70-(814) bb5: 60 %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0 68 %reg1027<def> = t2LDRi12 %reg1027<kill>, 8, 14, %reg0 76 t2CMPzri %reg1038<kill,undef>, 0, 14, %reg0, %CPSR<imp-def> 84 %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0 96 t2Bcc mbb<bb5,0x2030910>, 1, %CPSR<kill> Do not remove the kill marker on t2LDRi12. llvm-svn: 78178
* Fix a coaelescer bug. If a copy val# is extended to eliminate a ↵Evan Cheng2009-08-031-1/+8
| | | | | | non-trivially coalesced copy, and the copy kills its source register. Trim the source register's live range to the last use if possible. This fixes up kill marker to make the scavenger happy. llvm-svn: 77967
* Use setPreservesAll and setPreservesCFG in CodeGen passes.Dan Gohman2009-07-311-0/+1
| | | | llvm-svn: 77754
* inline the global 'getInstrOperandRegClass' function into its callersChris Lattner2009-07-291-1/+1
| | | | | | now that TargetOperandInfo does the heavy lifting. llvm-svn: 77508
* Avoid build warnings.Mike Stump2009-07-271-0/+1
| | | | llvm-svn: 77271
* More migration to raw_ostream, the water has dried up around the iostream hole.Daniel Dunbar2009-07-251-13/+14
| | | | | | | | | | - Some clients which used DOUT have moved to DEBUG. We are deprecating the "magic" DOUT behavior which avoided calling printing functions when the statement was disabled. In addition to being unnecessary magic, it had the downside of leaving code in -Asserts builds, and of hiding potentially unnecessary computations. llvm-svn: 77019
* Make some changes suggested by Bill and Evan.David Greene2009-07-221-17/+1
| | | | llvm-svn: 76775
* Add some support for iterative coalescers to calculate a joined liveDavid Greene2009-07-211-1/+18
| | | | | | | | | | range's weight properly. This is turned off right now in the sense that you'll get an assert if you get into a situation that can only be caused by an iterative coalescer. All other code paths operate exactly as before so there is no functional change with this patch. The asserts should be disabled if/when an iterative coalescer gets added to trunk. llvm-svn: 76680
* Cross RC coalescing is now on by default.Evan Cheng2009-07-211-4/+4
| | | | llvm-svn: 76519
* Fix some sub-reg coalescing bugs where the coalescer wasn't updating the ↵Evan Cheng2009-07-201-12/+18
| | | | | | resulting interval's register class. llvm-svn: 76458
* Catch more coalescing opportunities.Evan Cheng2009-07-181-4/+7
| | | | llvm-svn: 76282
* Enable cross register class coalescing.Evan Cheng2009-07-181-10/+21
| | | | llvm-svn: 76281
* Simplify some more.Evan Cheng2009-07-171-74/+5
| | | | llvm-svn: 76239
* Simplify the coalescer (finally!) by making ↵Evan Cheng2009-07-171-122/+2
| | | | | | LiveIntervals::processImplicitDefs a little more aggressive and teaching liveintervals to make use of isUndef marker on MachineOperands. llvm-svn: 76223
* Let callers decide the sub-register index on the def operand of ↵Evan Cheng2009-07-161-7/+8
| | | | | | | | rematerialized instructions. Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right. llvm-svn: 75900
* ShortenDeadCopySrcLiveRange needs to be more conservative in multi-kill ↵Evan Cheng2009-07-151-1/+6
| | | | | | situations. llvm-svn: 75838
* llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.Torok Edwin2009-07-141-2/+2
| | | | | | | | | This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). llvm-svn: 75640
* Fix pr4544. When remating, make sure the destination register fits the ↵Evan Cheng2009-07-141-0/+11
| | | | | | | | instruction definition. It may be mismatched due to sub-register coalescing. No test case yet because the code doesn't trigger until 75408 is re-applied. llvm-svn: 75572
* assert(0) -> LLVM_UNREACHABLE.Torok Edwin2009-07-111-3/+3
| | | | | | | | | Make llvm_unreachable take an optional string, thus moving the cerr<< out of line. LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for NDEBUG builds. llvm-svn: 75379
* Remove TargetInstrInfo::CommuteChangesDestination and added ↵Evan Cheng2009-07-101-3/+17
| | | | | | findCommutedOpIndices which returns the operand indices which are swapped (when applicable). This allows for some code clean up and future enhancements. llvm-svn: 75264
* Improved tracking of value number kills. VN kills are now representedLang Hames2009-07-091-9/+7
| | | | | | | | | | | | as an (index,bool) pair. The bool flag records whether the kill is a PHI kill or not. This code will be used to enable splitting of live intervals containing PHI-kills. A slight change to live interval weights introduced an extra spill into lsr-code-insertion (outside the critical sections). The test condition has been updated to reflect this. llvm-svn: 75097
* Remove special handling of implicit_def. Fix a couple more bugs in ↵Evan Cheng2009-07-011-5/+14
| | | | | | | | liveintervalanalysis and coalescer handling of implicit_def. Note, isUndef marker must be placed even on implicit_def def operand or else the scavenger will not ignore it. This is necessary because -O0 path does not use liveintervalanalysis, it treats implicit_def just like any other def. llvm-svn: 74601
* Fix another register coalescer crash: forgot to check if the instruction ↵Evan Cheng2009-06-221-3/+7
| | | | | | being updated has already been coalesced. llvm-svn: 73898
* - Update register allocation hint after coalescing. This is done by the ↵Evan Cheng2009-06-181-0/+3
| | | | | | | | | target since the hint is target dependent. This is important for ARM register pair hints. - Register allocator should resolve the second part of the hint (register number) before passing it to the target since it knows virtual register to physical register mapping. - More fixes to get ARM load / store double word working. llvm-svn: 73671
* VNInfo cleanup.Lang Hames2009-06-171-22/+32
| | | | llvm-svn: 73634
* Rename RemoveCopiesFromValNo to TurnCopiesFromValNoToImpDefs.Evan Cheng2009-06-161-6/+6
| | | | llvm-svn: 73479
* If a val# is defined by an implicit_def and it is being removed, all of the ↵Evan Cheng2009-06-161-20/+27
| | | | | | | | copies off the val# were removed. This causes problem later since the scavenger will see uses of registers without defs. The proper solution is to change the copies into implicit_def's instead. TurnCopyIntoImpDef turns a copy into implicit_def and remove the val# defined by it. This causes an scavenger assertion later if the def reaches other blocks. Disable the transformation if the value live interval extends beyond its def block. llvm-svn: 73478
* Part 1.Evan Cheng2009-06-151-36/+11
| | | | | | | | | | | | | | | | | | | | | - Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. llvm-svn: 73381
* Move register allocation preference (or hint) from LiveInterval to ↵Evan Cheng2009-06-141-12/+59
| | | | | | MachineRegisterInfo. This allows more passes to set them. llvm-svn: 73346
* Update to in-place spilling framework. Includes live interval scaling and ↵Lang Hames2009-06-021-1/+1
| | | | | | trivial rewriter. llvm-svn: 72729
* Fixed PR4090.Lang Hames2009-05-111-1/+16
| | | | llvm-svn: 71495
* Join cross class copies using getCommonSubClass()Jakob Stoklund Olesen2009-04-301-20/+8
| | | | llvm-svn: 70513
* Add a smarter heuristic to determine when to coalesce a virtual register ↵Evan Cheng2009-04-301-20/+161
| | | | | | | | with a physical one. More specifically, it avoid tying a virtual register in the loop with a physical register defined / used outside the loop. When it determines it's not profitable, it will use the physical register as the allocation preference instead. This is *not* turned on by default. Testing indicates this is just as likely to pessimize code. The main issue seems to be allocation preference doesn't work effectively. That will change once I've taught register allocator "swapping". llvm-svn: 70503
* Move getMatchingSuperReg() out of coalescer and into TargetRegisterInfo.Evan Cheng2009-04-281-16/+4
| | | | llvm-svn: 70309
* Don't coalesce a physical register with an incompatible virtual register.Jakob Stoklund Olesen2009-04-281-5/+42
| | | | | | | | | | If the physical register does not belong to the virtual register's regclass, don't coalesce. The physical register could be an invalid operand for an instruction using the vreg. The regclass matching is done after determining the actual subregisters being copied. llvm-svn: 70298
* Don't skip the CopyMI when removing kill markers.Owen Anderson2009-04-271-2/+0
| | | | | | | This should have no effect on generated code, but makes the intermediate state of the coalescer more sane. llvm-svn: 70238
* Update comments.Evan Cheng2009-04-231-2/+2
| | | | llvm-svn: 69919
* Fix an obvious type.Evan Cheng2009-04-231-1/+1
| | | | llvm-svn: 69918
* Implement support for using modeling implicit-zero-extension on x86-64Dan Gohman2009-04-081-24/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG instructions), and teach the DAGCombiner to take advantage of this on targets which support it. This eliminates many redundant zero-extension operations on x86-64. This adds a new TargetLowering hook, isZExtFree. It's similar to isTruncateFree, except it only applies to actual definitions, and not no-op truncates which may not zero the high bits. Also, this adds a new optimization to SimplifyDemandedBits: transform operations like x+y into (zext (add (trunc x), (trunc y))) on targets where all the casts are no-ops. In contexts where the high part of the add is explicitly masked off, this allows the mask operation to be eliminated. Fix the DAGCombiner to avoid undoing these transformations to eliminate casts on targets where the casts are no-ops. Also, this adds a new two-address lowering heuristic. Since two-address lowering runs before coalescing, it helps to be able to look through copies when deciding whether commuting and/or three-address conversion are profitable. Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle the case that a clobber range extended both before and beyond an existing live range. In that case, multiple live ranges need to be added. This was exposed by the new subreg coalescing code. Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the spiller behavior it was looking for no longer occurrs with the new instruction selection. llvm-svn: 68576
* Fix grammar-o in comment.Bill Wendling2009-03-301-1/+1
| | | | llvm-svn: 68057
* My last coalescer fix introduced a subtler one. It's aborting a commuting ↵Evan Cheng2009-03-111-5/+11
| | | | | | optimization too late and left the live intervals to be out of sync with instructions. This fixes 8b10b. llvm-svn: 66715
* Two coalescer fixes in one.Evan Cheng2009-03-111-6/+20
| | | | | | | 1. Use the same value# to represent unknown values being merged into sub-registers. 2. When coalescer commute an instruction and the destination is a physical register, update its sub-registers by merging in the extended ranges. llvm-svn: 66610
* If a use operand is marked isKill, don't forget to add kill to its live ↵Evan Cheng2009-02-221-4/+6
| | | | | | interval as well. llvm-svn: 65279
* Fix another case ShortenDeadCopySrcLiveRange is shortening too much. No test ↵Evan Cheng2009-02-091-6/+13
| | | | | | case possible since I don't know what to grep for. :-( llvm-svn: 64125
* Fix PR3486. Fix a bug in code that manually patch physical register live ↵Evan Cheng2009-02-081-14/+25
| | | | | | interval after its sub-register is coalesced with a virtual register. llvm-svn: 64082
* Strengthen the previous check.Evan Cheng2009-02-081-4/+5
| | | | llvm-svn: 64076
OpenPOWER on IntegriCloud