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* While legalizing SDValues do not drop SDDbgValues, trasfer them to new legal ↵Devang Patel2011-01-272-1/+4
| | | | | | | | nodes. Take 2. This includes fix for dragonegg crash. llvm-svn: 124380
* Try harder to not have unused variables.Matt Beaumont-Gay2011-01-271-0/+2
| | | | llvm-svn: 124350
* Opt-mode -Wunused-variable cleanupMatt Beaumont-Gay2011-01-271-4/+2
| | | | llvm-svn: 124346
* Reapply 124301Devang Patel2011-01-271-1/+5
| | | | llvm-svn: 124339
* Initialize variable to get rid of clang warning.Bill Wendling2011-01-261-1/+1
| | | | llvm-svn: 124331
* Revert 124301.Devang Patel2011-01-261-5/+1
| | | | llvm-svn: 124327
* Revert r124302Devang Patel2011-01-261-3/+0
| | | | llvm-svn: 124320
* [AVX] Add INSERT_SUBVECTOR and support it on x86. This provides aDavid Greene2011-01-262-0/+73
| | | | | | | | default implementation for x86, going through the stack in a similr fashion to how the codegen implements BUILD_VECTOR. Eventually this will get matched to VINSERTF128 if AVX is available. llvm-svn: 124307
* While legalizing SDValues do not drop SDDbgValues, trasfer them to new legal ↵Devang Patel2011-01-261-0/+3
| | | | | | nodes. llvm-svn: 124302
* Process valid SDDbgValues even if the node does not have any order assigned.Devang Patel2011-01-261-1/+5
| | | | llvm-svn: 124301
* Refactor.Devang Patel2011-01-261-19/+30
| | | | llvm-svn: 124300
* [AVX] Support EXTRACT_SUBVECTOR on x86. This provides a defaultDavid Greene2011-01-262-5/+24
| | | | | | | | implementation of EXTRACT_SUBVECTOR for x86, going through the stack in a similr fashion to how the codegen implements BUILD_VECTOR. Eventually this will get matched to VEXTRACTF128 if AVX is available. llvm-svn: 124292
* Provide an interface to transfer SDDbgValue from one SDNode to another.Devang Patel2011-01-252-0/+25
| | | | llvm-svn: 124245
* Resolve DanglingDbgValue of PHI nodes where the use follows dbg.value ↵Devang Patel2011-01-251-1/+3
| | | | | | intrinisic. llvm-svn: 124203
* This assertion is too restrictive, it does not apply for dangling dbg value ↵Devang Patel2011-01-251-8/+0
| | | | | | nodes (nodes where dbg.value intrinsic preceds use of the value). llvm-svn: 124202
* Speculatively revert r124138.Devang Patel2011-01-241-3/+1
| | | | llvm-svn: 124142
* Resolve DanglingDbgValue of PHI nodes where the use follows dbg.value ↵Devang Patel2011-01-241-1/+3
| | | | | | intrinisic. llvm-svn: 124138
* Temporarily workaround JM/lencod miscompile (SIGSEGV).Andrew Trick2011-01-241-0/+2
| | | | | | rdar://problem/8893967 llvm-svn: 124137
* Null initialize a few variables flagged byTed Kremenek2011-01-231-1/+1
| | | | | | | | | | clang's -Wuninitialized-experimental warning. While these don't look like real bugs, clang's -Wuninitialized-experimental analysis is stricter than GCC's, and these fixes have the benefit of being general nice cleanups. llvm-svn: 124073
* Enable support for precise scheduling of the instruction selectionAndrew Trick2011-01-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | DAG. Disable using "-disable-sched-cycles". For ARM, this enables a framework for modeling the cpu pipeline and counting stalls. It also activates several heuristics to drive scheduling based on the model. Scheduling is inherently imprecise at this stage, and until spilling is improved it may defeat attempts to schedule. However, this framework provides greater control over tuning codegen. Although the flag is not target-specific, it should have very little affect on the default scheduler used by x86. The only two changes that affect x86 are: - scheduling a high-latency operation bumps the current cycle so independent operations can have their latency covered. i.e. two independent 4 cycle operations can produce results in 4 cycles, not 8 cycles. - Two operations with equal register pressure impact and no latency-based stalls on their uses will be prioritized by depth before height (height is irrelevant if no stalls occur in the schedule below this point). llvm-svn: 123971
* Convert -enable-sched-cycles and -enable-sched-hazard to -disableAndrew Trick2011-01-211-29/+31
| | | | | | | | | | | flags. They are still not enable in this revision. Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with the scheduler's model of operand latency in the selection DAG. Generalized unit tests to work with sched-cycles. llvm-svn: 123969
* My editor's indent went crazy. Fix.Eric Christopher2011-01-201-1/+1
| | | | llvm-svn: 123909
* Expand invalid return values for umulo and smulo. Handle these similarlyEric Christopher2011-01-202-0/+28
| | | | | | | | | | to add/sub by doing the normal operation and then checking for overflow afterwards. This generally relies on the DAG handling the later invalid operations as well. Fixes the 64-bit part of rdar://8622122 and rdar://8774702. llvm-svn: 123908
* Selection DAG scheduler register pressure heuristic fixes.Andrew Trick2011-01-201-8/+27
| | | | | | | | Added a check for already live regs before claiming HighRegPressure. Fixed a few cases of checking the wrong number of successors. Added some tracing until these heuristics are better understood. llvm-svn: 123892
* Use only one API at a time.Eric Christopher2011-01-201-2/+1
| | | | llvm-svn: 123866
* If we can, lower the multiply part of a umulo/smulo call to a libcallEric Christopher2011-01-201-8/+27
| | | | | | | | | with an invalid type then split the result and perform the overflow check normally. Fixes the 32-bit parts of rdar://8622122 and rdar://8774702. llvm-svn: 123864
* Remove unused variables found by gcc-4.6's -Wunused-but-set-variable.Jeffrey Yasskin2011-01-181-1/+0
| | | | llvm-svn: 123707
* Remove checking that prevented overlapping CALLSEQ_START/CALLSEQ_ENDStuart Hastings2011-01-181-15/+9
| | | | | | | ranges, add legalizer support for nested calls. Necessary for ARM byval support. Radar 7662569. llvm-svn: 123704
* Fix an off-by-one error in ctpop combining.Benjamin Kramer2011-01-171-1/+1
| | | | llvm-svn: 123664
* Add a DAGCombine to turn (ctpop x) u< 2 into (x & x-1) == 0.Benjamin Kramer2011-01-171-0/+24
| | | | | | | | | This shaves off 4 popcounts from the hacked 186.crafty source. This is enabled even when a native popcount instruction is available. The combined code is one operation longer but it should be faster nevertheless. llvm-svn: 123621
* reapply my fix for PR8961 with a tweak to properly handleChris Lattner2011-01-161-6/+12
| | | | | | | multi-instruction sequences like calls. Many thanks to Jakob for finding a testcase. llvm-svn: 123559
* Add an assert so we don't silently miscompile ctpop for bit widths > 128.Benjamin Kramer2011-01-151-0/+4
| | | | llvm-svn: 123549
* Reimplement CTPOP legalization with the "best" algorithm fromBenjamin Kramer2011-01-151-18/+45
| | | | | | | | | | | | | http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel In a silly microbenchmark on a 65 nm core2 this is 1.5x faster than the old code in 32 bit mode and about 2x faster in 64 bit mode. It's also a lot shorter, especially when counting 64 bit population on a 32 bit target. I hope this is fast enough to replace Kernighan-style counting loops even when the input is rather sparse. llvm-svn: 123547
* Delete an assignment to ThisBB which isn't needed, and tidy up someDan Gohman2011-01-141-4/+6
| | | | | | comments. llvm-svn: 123479
* Support for precise scheduling of the instruction selection DAG,Andrew Trick2011-01-141-537/+663
| | | | | | | | | | | | | | | | | | | | | | | | | disabled in this checkin. Sorry for the large diffs due to refactoring. New functionality is all guarded by EnableSchedCycles. Scheduling the isel DAG is inherently imprecise, but we give it a best effort: - Added MayReduceRegPressure to allow stalled nodes in the queue only if there is a regpressure need. - Added BUHasStall to allow checking for either dependence stalls due to latency or resource stalls due to pipeline hazards. - Added BUCompareLatency to encapsulate and standardize the heuristics for minimizing stall cycles (vs. reducing register pressure). - Modified the bottom-up heuristic (now in BUCompareLatency) to prioritize nodes by their depth rather than height. As long as it doesn't stall, height is irrelevant. Depth represents the critical path to the DAG root. - Added hybrid_ls_rr_sort::isReady to filter stalled nodes before adding them to the available queue. Related Cleanup: most of the register reduction routines do not need to be templates. llvm-svn: 123468
* Set the insertion point correctly for instructions generated by load folding:Chris Lattner2011-01-141-4/+4
| | | | | | they should go *before* the new instruction not after it. llvm-svn: 123420
* Fix r123346 to handle scalar types too.Dan Gohman2011-01-131-2/+1
| | | | llvm-svn: 123352
* Apply the patch from PR8958, which allows llc to get slightlyDan Gohman2011-01-121-1/+2
| | | | | | further on the associated testcase before aborting. llvm-svn: 123346
* Move ExpandAtomic into the integer expansion routines - it's only used there.Eric Christopher2011-01-112-86/+87
| | | | llvm-svn: 123202
* Fix PR 8916 (qv for analysis), at least the immediate problem.Dale Johannesen2011-01-101-1/+2
| | | | | | | | | | | There's an inherent tension in DAGCombine between assuming that things will be put in canonical form, and the Depth mechanism that disables transformations when recursion gets too deep. It would not surprise me if there's a lot of little bugs like this one waiting to be discovered. The mechanism seems fragile and I'd suggest looking at it from a design viewpoint. llvm-svn: 123191
* Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov2011-01-105-7/+4
| | | | | | and fixes here and there. llvm-svn: 123170
* Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.Jakob Stoklund Olesen2011-01-102-2/+2
| | | | | | | | These functions not longer assert when passed 0, but simply return false instead. No functional change intended. llvm-svn: 123155
* Replace TargetRegisterInfo::printReg with a PrintReg class that also works ↵Jakob Stoklund Olesen2011-01-091-6/+1
| | | | | | | | | | without a TRI instance. Print virtual registers numbered from 0 instead of the arbitrary FirstVirtualRegister. The first virtual register is printed as %vreg0. TRI::NoRegister is printed as %noreg. llvm-svn: 123107
* Use an IndexedMap for LiveOutRegInfo to hide its dependence on ↵Jakob Stoklund Olesen2011-01-082-9/+4
| | | | | | TargetRegisterInfo::FirstVirtualRegister. llvm-svn: 123096
* Do not model all INLINEASM instructions as having unmodelled side effects.Evan Cheng2011-01-073-12/+15
| | | | | | | | | | Instead encode llvm IR level property "HasSideEffects" in an operand (shared with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check the operand when the instruction is an INLINEASM. This allows memory instructions to be moved around INLINEASM instructions. llvm-svn: 123044
* Add ARM patterns to match EXTRACT_SUBVECTOR nodes.Bob Wilson2011-01-071-1/+1
| | | | | | | | | | | | | | | Also fix an off-by-one in SelectionDAGBuilder that was preventing shuffle vectors from being translated to EXTRACT_SUBVECTOR. Patch by Tim Northover. The test changes are needed to keep those spill-q tests from testing aligned spills and restores. If the only aligned stack objects are spill slots, we no longer realign the stack frame. Prior to this patch, an EXTRACT_SUBVECTOR was legalized by loading from the stack, which created an aligned frame index. Now, however, there is nothing except the spill slot in the stack frame, so I added an aligned alloca. llvm-svn: 122995
* Change EXTRACT_SUBVECTOR to require a constant index.Bob Wilson2011-01-071-32/+16
| | | | | | | | We were never generating any of these nodes with variable indices, and there was one legalizer function asserting on a non-constant index. If we ever have a need to support variable indices, we can add this back again. llvm-svn: 122993
* Fix the other problem reported in PR8582. Testcase and patch byDuncan Sands2011-01-061-0/+5
| | | | | | Nadav Rotem. llvm-svn: 122983
* Add some fairly duplicated code to let type legalization split illegalEric Christopher2011-01-063-0/+141
| | | | | | typed atomics. This will lower exclusively to libcalls at the moment. llvm-svn: 122979
* Re-implement r122936 with proper target hooks. Now getMaxStoresPerMemcpyEvan Cheng2011-01-062-15/+14
| | | | | | | etc. takes an option OptSize. If OptSize is true, it would return the inline limit for functions with attribute OptSize. llvm-svn: 122952
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