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* Don't forget return void.Evan Cheng2006-04-251-0/+3
| | | | llvm-svn: 27974
* Fix the updating of the machine CFG when a PHI node was in a successor ofNate Begeman2006-04-231-5/+10
| | | | | | | the jump table's range check block. This re-enables 100% dense jump tables by default on PPC & x86 llvm-svn: 27952
* Turn of jump tables for a bit, there are still some issues to work out withNate Begeman2006-04-221-1/+1
| | | | | | updating the machine CFG. llvm-svn: 27949
* JumpTable support! What this represents is working asm and jit support forNate Begeman2006-04-224-8/+185
| | | | | | | | x86 and ppc for 100% dense switch statements when relocations are non-PIC. This support will be extended and enhanced in the coming days to support PIC, and less dense forms of jump tables. llvm-svn: 27947
* The BFS scheduler is apparently nondeterminstic (causes many llvmgcc bootstrapChris Lattner2006-04-211-2/+5
| | | | | | miscompares). Switch RISC targets to use the list-td scheduler, which isn't. llvm-svn: 27933
* Fix a couple more memory issuesChris Lattner2006-04-211-4/+4
| | | | llvm-svn: 27930
* Fix a really subtle and obnoxious memory bug that caused issues with anChris Lattner2006-04-201-11/+11
| | | | | | | | | llvm-gcc4 boostrap. Whenever a node is deleted by the dag combiner, it *must* be returned by the visit function, or the dag combiner will not know that the node has been processed (and will, e.g., send it to the target dag combine xforms). llvm-svn: 27922
* Turn a VAND into a VECTOR_SHUFFLE is applicable.Evan Cheng2006-04-201-1/+64
| | | | | | | | DAG combiner can turn a VAND V, <-1, 0, -1, -1>, i.e. vector clear elements, into a vector shuffle with a zero vector. It only does so when TLI tells it the xform is profitable. llvm-svn: 27874
* Implement folding of a bunch of binops with undefChris Lattner2006-04-201-0/+46
| | | | llvm-svn: 27863
* Simplify some codeChris Lattner2006-04-191-5/+1
| | | | llvm-svn: 27846
* Fix handling of calls in functions that use vectors. This fixes a crash onChris Lattner2006-04-171-13/+1
| | | | | | the code in GCC PR26546. llvm-svn: 27780
* Codegen insertelement with constant insertion points as scalar_to_vectorChris Lattner2006-04-171-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and a shuffle. For this: void %test2(<4 x float>* %F, float %f) { %tmp = load <4 x float>* %F ; <<4 x float>> [#uses=2] %tmp3 = add <4 x float> %tmp, %tmp ; <<4 x float>> [#uses=1] %tmp2 = insertelement <4 x float> %tmp3, float %f, uint 2 ; <<4 x float>> [#uses=2] %tmp6 = add <4 x float> %tmp2, %tmp2 ; <<4 x float>> [#uses=1] store <4 x float> %tmp6, <4 x float>* %F ret void } we now get this on X86 (which will get better): _test2: movl 4(%esp), %eax movaps (%eax), %xmm0 addps %xmm0, %xmm0 movaps %xmm0, %xmm1 shufps $3, %xmm1, %xmm1 movaps %xmm0, %xmm2 shufps $1, %xmm2, %xmm2 unpcklps %xmm1, %xmm2 movss 8(%esp), %xmm1 unpcklps %xmm1, %xmm0 unpcklps %xmm2, %xmm0 addps %xmm0, %xmm0 movaps %xmm0, (%eax) ret instead of: _test2: subl $28, %esp movl 32(%esp), %eax movaps (%eax), %xmm0 addps %xmm0, %xmm0 movaps %xmm0, (%esp) movss 36(%esp), %xmm0 movss %xmm0, 8(%esp) movaps (%esp), %xmm0 addps %xmm0, %xmm0 movaps %xmm0, (%eax) addl $28, %esp ret llvm-svn: 27765
* Add support for promoting stores from one legal type to another, allowing usChris Lattner2006-04-161-0/+8
| | | | | | to write one pattern for vector stores instead of 4. llvm-svn: 27730
* Make these predicates return true for bit_convert(buildvector)'s as well asChris Lattner2006-04-151-0/+8
| | | | | | buildvectors. llvm-svn: 27723
* Make this assertion betterChris Lattner2006-04-141-1/+1
| | | | llvm-svn: 27695
* Promote vector AND, OR, and XOREvan Cheng2006-04-121-0/+27
| | | | llvm-svn: 27632
* Vector type promotion for ISD::LOAD and ISD::SELECTEvan Cheng2006-04-121-9/+23
| | | | llvm-svn: 27606
* Implement support for the formal_arguments node. To get this, targets ↵Chris Lattner2006-04-123-3/+128
| | | | | | shouldcustom legalize it and remove their XXXTargetLowering::LowerArguments overload llvm-svn: 27604
* Don't memoize vloads in the load map! Don't memoize them anywhere here, letChris Lattner2006-04-121-2/+0
| | | | | | getNode do it. This fixes CodeGen/Generic/2006-04-11-vecload.ll llvm-svn: 27602
* Only get Tmp2 for cases where number of operands is > 1. Fixed return void.Evan Cheng2006-04-111-1/+1
| | | | llvm-svn: 27586
* add some todosChris Lattner2006-04-111-0/+8
| | | | llvm-svn: 27580
* Add basic support for legalizing returns of vectorsChris Lattner2006-04-111-9/+36
| | | | llvm-svn: 27578
* Missing breakEvan Cheng2006-04-101-0/+1
| | | | llvm-svn: 27559
* Add code generator support for VSELECTChris Lattner2006-04-083-10/+22
| | | | llvm-svn: 27542
* Canonicalize vvector_shuffle(x,x) -> vvector_shuffle(x,undef) to enable patternsChris Lattner2006-04-082-2/+50
| | | | | | to match again :) llvm-svn: 27533
* Codegen shufflevector as VVECTOR_SHUFFLEChris Lattner2006-04-082-2/+25
| | | | llvm-svn: 27529
* add a sanity check: LegalizeOp should return a value that is the same typeChris Lattner2006-04-081-0/+3
| | | | | | as its input. llvm-svn: 27528
* INSERT_VECTOR_ELT lowering bug:Evan Cheng2006-04-081-14/+11
| | | | | | | | | store vector to $esp store element to $esp + sizeof(VT) * index load vector from $esp The bug is VT is the type of the vector element, not the type of the vector! llvm-svn: 27517
* Stub out shufflevectorChris Lattner2006-04-081-0/+1
| | | | llvm-svn: 27514
* 1. If both vector operands of a vector_shuffle are undef, turn it into an undef.Evan Cheng2006-04-061-3/+6
| | | | | | 2. A shuffle mask element can also be an undef. llvm-svn: 27472
* Make a vector live across blocks have the correct Vec type. This fixesChris Lattner2006-04-051-1/+9
| | | | | | CodeGen/X86/2006-04-04-CrossBlockCrash.ll llvm-svn: 27436
* Exapnd a VECTOR_SHUFFLE to a BUILD_VECTOR if target asks for it to be expandedEvan Cheng2006-04-051-2/+30
| | | | | | or custom lowering fails. llvm-svn: 27432
* Do not create ZEXTLOAD's unless we are before legalize or the operation isChris Lattner2006-04-041-1/+2
| | | | | | legal. llvm-svn: 27402
* * Add supprot for SCALAR_TO_VECTOR operations where the input needs to beChris Lattner2006-04-041-21/+102
| | | | | | | | | | promoted/expanded (e.g. SCALAR_TO_VECTOR from i8/i16 on PPC). * Add support for targets to request that VECTOR_SHUFFLE nodes be promoted to a canonical type, for example, we only want v16i8 shuffles on PPC. * Move isShuffleLegal out of TLI into Legalize. * Teach isShuffleLegal to allow shuffles that need to be promoted. llvm-svn: 27399
* Constant fold bitconvert(undef)Chris Lattner2006-04-041-0/+2
| | | | llvm-svn: 27391
* Add a missing check, this fixes UnitTests/Vector/sumarray.cChris Lattner2006-04-031-2/+2
| | | | llvm-svn: 27375
* Add a missing check, which broke a bunch of vector tests.Chris Lattner2006-04-031-3/+6
| | | | llvm-svn: 27374
* back this outAndrew Lenharth2006-04-031-25/+0
| | | | llvm-svn: 27367
* This should be a win of every archAndrew Lenharth2006-04-021-1/+26
| | | | llvm-svn: 27364
* Add a little dag combine to compile this:Chris Lattner2006-04-021-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | int %AreSecondAndThirdElementsBothNegative(<4 x float>* %in) { entry: %tmp1 = load <4 x float>* %in ; <<4 x float>> [#uses=1] %tmp = tail call int %llvm.ppc.altivec.vcmpgefp.p( int 1, <4 x float> < float 0x7FF8000000000000, float 0.000000e+00, float 0.000000e+00, float 0x7FF8000000000000 >, <4 x float> %tmp1 ) ; <int> [#uses=1] %tmp = seteq int %tmp, 0 ; <bool> [#uses=1] %tmp3 = cast bool %tmp to int ; <int> [#uses=1] ret int %tmp3 } into this: _AreSecondAndThirdElementsBothNegative: mfspr r2, 256 oris r4, r2, 49152 mtspr 256, r4 li r4, lo16(LCPI1_0) lis r5, ha16(LCPI1_0) lvx v0, 0, r3 lvx v1, r5, r4 vcmpgefp. v0, v1, v0 mfcr r3, 2 rlwinm r3, r3, 27, 31, 31 mtspr 256, r2 blr instead of this: _AreSecondAndThirdElementsBothNegative: mfspr r2, 256 oris r4, r2, 49152 mtspr 256, r4 li r4, lo16(LCPI1_0) lis r5, ha16(LCPI1_0) lvx v0, 0, r3 lvx v1, r5, r4 vcmpgefp. v0, v1, v0 mfcr r3, 2 rlwinm r3, r3, 27, 31, 31 xori r3, r3, 1 cntlzw r3, r3 srwi r3, r3, 5 mtspr 256, r2 blr llvm-svn: 27356
* Implement promotion for EXTRACT_VECTOR_ELT, allowing v16i8 multiplies to ↵Chris Lattner2006-04-021-16/+27
| | | | | | work with PowerPC. llvm-svn: 27349
* Implement the Expand action for binary vector operations to break the binopChris Lattner2006-04-021-1/+18
| | | | | | | into elements and operate on each piece. This allows generic vector integer multiplies to work on PPC, though the generated code is horrible. llvm-svn: 27347
* Intrinsics that just load from memory can be treated like loads: they don'tChris Lattner2006-04-021-4/+25
| | | | | | | have to serialize against each other. This allows us to schedule lvx's across each other, for example. llvm-svn: 27346
* Constant fold all of the vector binops. This allows us to compile this:Chris Lattner2006-04-021-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "vector unsigned char mergeLowHigh = (vector unsigned char) ( 8, 9, 10, 11, 16, 17, 18, 19, 12, 13, 14, 15, 20, 21, 22, 23 ); vector unsigned char mergeHighLow = vec_xor( mergeLowHigh, vec_splat_u8(8));" aka: void %test2(<16 x sbyte>* %P) { store <16 x sbyte> cast (<4 x int> xor (<4 x int> cast (<16 x ubyte> < ubyte 8, ubyte 9, ubyte 10, ubyte 11, ubyte 16, ubyte 17, ubyte 18, ubyte 19, ubyte 12, ubyte 13, ubyte 14, ubyte 15, ubyte 20, ubyte 21, ubyte 22, ubyte 23 > to <4 x int>), <4 x int> cast (<16 x sbyte> < sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8 > to <4 x int>)) to <16 x sbyte>), <16 x sbyte> * %P ret void } into this: _test2: mfspr r2, 256 oris r4, r2, 32768 mtspr 256, r4 li r4, lo16(LCPI2_0) lis r5, ha16(LCPI2_0) lvx v0, r5, r4 stvx v0, 0, r3 mtspr 256, r2 blr instead of this: _test2: mfspr r2, 256 oris r4, r2, 49152 mtspr 256, r4 li r4, lo16(LCPI2_0) lis r5, ha16(LCPI2_0) vspltisb v0, 8 lvx v1, r5, r4 vxor v0, v1, v0 stvx v0, 0, r3 mtspr 256, r2 blr ... which occurs here: http://developer.apple.com/hardware/ve/calcspeed.html llvm-svn: 27343
* Add a new -view-legalize-dags command line optionChris Lattner2006-04-022-3/+13
| | | | llvm-svn: 27342
* Implement constant folding of bit_convert of arbitrary constant ↵Chris Lattner2006-04-021-2/+139
| | | | | | vbuild_vector nodes. llvm-svn: 27341
* These entries already existChris Lattner2006-04-021-4/+0
| | | | llvm-svn: 27340
* Add some missing node namesChris Lattner2006-04-021-0/+9
| | | | llvm-svn: 27339
* Prefer larger register classes over smaller ones when a register occurs inChris Lattner2006-04-021-7/+21
| | | | | | multiple register classes. This fixes PowerPC/2006-04-01-FloatDoubleExtend.ll llvm-svn: 27334
* Delete identity shuffles, implementing ↵Chris Lattner2006-03-311-2/+56
| | | | | | CodeGen/Generic/vector-identity-shuffle.ll llvm-svn: 27317
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