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* Added basic support for expanding VSETCCMon P Wang2008-12-131-2/+21
| | | | llvm-svn: 60974
* On big-endian machines it is wrong to do a fullDuncan Sands2008-12-131-19/+22
| | | | | | | | | | width register load followed by a truncating store for the copy, since the load will not place the value in the lower bits. Probably partial loads/stores can never happen here, but fix it anyway. llvm-svn: 60972
* When expanding unaligned loads and stores do not makeDuncan Sands2008-12-121-34/+123
| | | | | | | | | | | | | | | | | | | | | | | | use of illegal integer types: instead, use a stack slot and copying via integer registers. The existing code is still used if the bitconvert is to a legal integer type. This fires on the PPC testcases 2007-09-08-unaligned.ll and vec_misaligned.ll. It looks like equivalent code is generated with these changes, just permuted, but it's hard to tell. With these changes, nothing in LegalizeDAG produces illegal integer types anymore. This is a prerequisite for removing the LegalizeDAG type legalization code. While there I noticed that the existing code doesn't handle trunc store of f64 to f32: it turns this into an i64 store, which represents a 4 byte stack smash. I added a FIXME about this. Hopefully someone more motivated than I am will take care of it. llvm-svn: 60964
* Fix add/sub expansion: don't create ADD / SUB with two results (seems like ↵Evan Cheng2008-12-121-5/+5
| | | | | | everyone is doing this these days :-). Patch by Daniel M Gessel! llvm-svn: 60958
* When using a 4 byte jump table on a 64 bit machine,Duncan Sands2008-12-121-11/+3
| | | | | | | | do an extending load of the 4 bytes rather than a potentially illegal (type) i32 load followed by a sign extend. llvm-svn: 60945
* Added support for SELECT v8i8 v4i16 for X86 (MMX)Mon P Wang2008-12-121-0/+4
| | | | | | Added support for TRUNC v8i16 to v8i8 for X86 (MMX) llvm-svn: 60916
* Redo the arithmetic with overflow architecture. I was changing the semantics ofBill Wendling2008-12-121-15/+0
| | | | | | | | | | | | ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. llvm-svn: 60915
* Avoid generating a convert_rndsat node when the src and dest type are the same.Mon P Wang2008-12-111-0/+4
| | | | llvm-svn: 60869
* Clarify FIXME.Bill Wendling2008-12-111-6/+6
| | | | llvm-svn: 60867
* Whitespace clean up (tabs with spaces)Mon P Wang2008-12-111-8/+8
| | | | llvm-svn: 60866
* Make fix for r60829 less conservative to allow the proper optimization forMon P Wang2008-12-111-2/+9
| | | | | | vec_extract-sse4.ll. llvm-svn: 60865
* If ADD, SUB, or MUL have an overflow bit that's used, don't do transformation onBill Wendling2008-12-101-0/+15
| | | | | | | them. The DAG combiner expects that nodes that are transformed have one value result. llvm-svn: 60857
* For amusement, implement SADDO, SSUBO, UADDO, USUBODuncan Sands2008-12-102-19/+80
| | | | | | | | | for promoted integer types, eg: i16 on ppc-32, or i24 on any platform. Complete support for arbitrary precision integers would require handling expanded integer types, eg: i128, but I couldn't be bothered. llvm-svn: 60834
* Fixed a bug when trying to optimize a extract vector element of aMon P Wang2008-12-101-1/+2
| | | | | | bit convert that changes the number of elements of a shuffle. llvm-svn: 60829
* Whitespace changes.Bill Wendling2008-12-101-1/+1
| | | | llvm-svn: 60826
* Whitespace fixes.Bill Wendling2008-12-101-14/+12
| | | | llvm-svn: 60818
* Rewrite the SDep class, and simplify some of the related code.Dan Gohman2008-12-094-221/+232
| | | | | | | | | | | | | | | | | The Cost field is removed. It was only being used in a very limited way, to indicate when the scheduler should attempt to protect a live register, and it isn't really needed to do that. If we ever want the scheduler to start inserting copies in non-prohibitive situations, we'll have to rethink some things anyway. A Latency field is added. Instead of giving each node a single fixed latency, each edge can have its own latency. This will eventually be used to model various micro-architecture properties more accurately. The PointerIntPair class and an internal union are now used, which reduce the overall size. llvm-svn: 60806
* Add sub/mul overflow intrinsics. This currently doesn't have aBill Wendling2008-12-096-25/+87
| | | | | | | target-independent way of determining overflow on multiplication. It's very tricky. Patch by Zoltan Varga! llvm-svn: 60800
* Fix PR3117: not all nodes being legalized. TheDuncan Sands2008-12-097-207/+467
| | | | | | | | | | | | | | | | | | | | | | | essential problem was that the DAG can contain random unused nodes which were never analyzed. When remapping a value of a node being processed, such a node may become used and need to be analyzed; however due to operands being transformed during analysis the node may morph into a different one. Users of the morphing node need to be updated, and this wasn't happening. While there I added a bunch of documentation and sanity checks, so I (or some other poor soul) won't have to scratch their head over this stuff so long trying to remember how it was all supposed to work next time some obscure problem pops up! The extra sanity checking exposed a few places where invariants weren't being preserved, so those are fixed too. Since some of the sanity checking is expensive, I added a flag to turn it on. It is also turned on when building with ENABLE_EXPENSIVE_CHECKS=1. llvm-svn: 60797
* In LegalizeOp, don't change the result type of CONVERT_RNDSAT when promotingMon P Wang2008-12-091-2/+2
| | | | | | one of its operand. llvm-svn: 60749
* Fix getNode to allow a vector for the shift amount for shifts of vectors.Mon P Wang2008-12-092-9/+33
| | | | | | | | Fix the shift amount when unrolling a vector shift into scalar shifts. Fix problem in getShuffleScalarElt where it assumes that the input of a bit convert must be a vector. llvm-svn: 60740
* Factor out the code for sign-extending/truncating gep indicesDan Gohman2008-12-081-23/+32
| | | | | | | | | and use it in x86 address mode folding. Also, make getRegForValue return 0 for illegal types even if it has a ValueMap for them, because Argument values are put in the ValueMap. This fixes PR3181. llvm-svn: 60696
* When allocating a stack temporary, use the correctDuncan Sands2008-12-041-1/+1
| | | | | | | number of bytes for types such as i1 which are not a multiple of 8 bits in length. llvm-svn: 60543
* Make debug output more informative.Dan Gohman2008-12-041-1/+1
| | | | llvm-svn: 60524
* Only check that the result of the mapping was notDuncan Sands2008-12-031-0/+1
| | | | | | a new node if the node was actually remapped. llvm-svn: 60482
* Remove a (what appears to be) overly strict assertion. Here is what happened:Evan Cheng2008-12-021-1/+0
| | | | | | | | | | | 1. ppcf128 select is expanded to f64 select's. 2. f64 select operand 0 is an i1 truncate, it's promoted to i32 zero_extend. 3. f64 select is updated. It's changed back to a "NewNode" and being re-analyzed. 4. f64 select operands are being processed. Operand 0 is a "NewNode". It's being expunged out of ReplacedValues map. 5. ExpungeNode tries to remap f64 select and notice it's a "NewNode" and assert. Duncan, please take a look. Thanks. llvm-svn: 60443
* Non-functional change: make custom lowering for truncate stylisticallyScott Michel2008-12-021-5/+12
| | | | | | consistent with the way it's generally done in other places. llvm-svn: 60439
* One more transformation.Dale Johannesen2008-12-021-0/+8
| | | | llvm-svn: 60432
* make it possible to custom lower TRUNCATE (needed for the CellSPU target)Tilmann Scheller2008-12-021-0/+5
| | | | llvm-svn: 60409
* Removed some unnecessary code in widening.Mon P Wang2008-12-021-115/+9
| | | | llvm-svn: 60406
* Add a few more transformations.Dale Johannesen2008-12-021-0/+24
| | | | llvm-svn: 60391
* Expand getVTList, getNodeValueTypes, and SelectNodeTo to handle more value ↵Bill Wendling2008-12-011-0/+33
| | | | | | types. llvm-svn: 60381
* There are no longer any places that require aDuncan Sands2008-12-013-18/+26
| | | | | | | | MERGE_VALUES node with only one operand, so get rid of special code that only existed to handle that possibility. llvm-svn: 60349
* Change the interface to the type legalization methodDuncan Sands2008-12-015-72/+34
| | | | | | | | | | | ReplaceNodeResults: rather than returning a node which must have the same number of results as the original node (which means mucking around with MERGE_VALUES, and which is also easy to get wrong since SelectionDAG folding may mean you don't get the node you expect), return the results in a vector. llvm-svn: 60348
* Followup to r60283: optimize arbitrary width signed divisions as well Eli Friedman2008-11-301-71/+34
| | | | | | as unsigned divisions. Same caveats as before. llvm-svn: 60284
* Fix for PR2164: allow transforming arbitrary-width unsigned divides intoEli Friedman2008-11-301-95/+65
| | | | | | | | | | | multiplies. Some more cleverness would be nice, though. It would be nice if we could do this transformation on illegal types. Also, we would prefer a narrower constant when possible so that we can use a narrower multiply, which can be cheaper. llvm-svn: 60283
* APIntify a test which is potentially unsafe otherwise, and fix the Eli Friedman2008-11-301-3/+10
| | | | | | | | | nearby FIXME. I'm not sure what the right way to fix the Cell test was; if the approach I used isn't okay, please let me know. llvm-svn: 60277
* Removing redundant semicolons. No functionality change.Sanjiv Gupta2008-11-271-2/+2
| | | | llvm-svn: 60149
* Add a missing case in visitADD.Dale Johannesen2008-11-271-0/+3
| | | | llvm-svn: 60137
* Allow custom lowering of ADDE/ADDC/SUBE/SUBC operations.Sanjiv Gupta2008-11-261-6/+36
| | | | llvm-svn: 60102
* A simplification for checking whether the signs of the operands and sum ↵Bill Wendling2008-11-251-15/+14
| | | | | | differ. Thanks, Duncan. llvm-svn: 60043
* Now with the correct type for the 0.Bill Wendling2008-11-251-1/+1
| | | | llvm-svn: 60016
* Get rid of unused variable.Bill Wendling2008-11-251-1/+0
| | | | llvm-svn: 60015
* Hacker's Delight says, "Signed integer overflow of addition occurs if and onlyBill Wendling2008-11-251-4/+48
| | | | | | | if the operands have the same sign and the sum has sign opposite to that of the operands." llvm-svn: 60014
* Initial support for anti-dependence breaking. Currently this code does notDan Gohman2008-11-251-238/+26
| | | | | | | | | introduce any new spilling; it just uses unused registers. Refactor the SUnit topological sort code out of the RRList scheduler and make use of it to help with the post-pass scheduler. llvm-svn: 59999
* - Make lowering of "add with overflow" customizable by back-ends.Bill Wendling2008-11-242-18/+29
| | | | | | | - Mark "add with overflow" as having a custom lowering for X86. Give it a null lowering representation for now. llvm-svn: 59971
* Check in the rest of this change. The isAntiDep flag needs to be passedDan Gohman2008-11-242-2/+2
| | | | | | | to removePred because an SUnit can both data-depend and anti-depend on the same SUnit. llvm-svn: 59969
* If the type legalizer actually legalized anythingDuncan Sands2008-11-244-195/+234
| | | | | | | | | | | | | (this doesn't happen that often, since most code does not use illegal types) then follow it by a DAG combiner run that is allowed to generate illegal operations but not illegal types. I didn't modify the target combiner code to distinguish like this between illegal operations and illegal types, so it will not produce illegal operations as well as not producing illegal types. llvm-svn: 59960
* Eliminate some unused variable compile time warnings.Evan Cheng2008-11-243-0/+9
| | | | llvm-svn: 59952
* Add support for llvm.uadd.with.overflow.Bill Wendling2008-11-241-5/+5
| | | | llvm-svn: 59926
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