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* Remove unneeded includes from FunctionLoweringInfo.h.Jakub Staszak2013-01-101-1/+1
| | | | llvm-svn: 172123
* Stack Alignment: throw error if we can't satisfy the minimal alignmentManman Ren2013-01-102-2/+4
| | | | | | | | | | | | | | | | | | requirement when creating stack objects in MachineFrameInfo. Add CreateStackObjectWithMinAlign to throw error when the minimal alignment can't be achieved and to clamp the alignment when the preferred alignment can't be achieved. Same is true for CreateVariableSizedObject. Will not emit error in CreateSpillStackObject or CreateStackObject. As long as callers of CreateStackObject do not assume the object will be aligned at the requested alignment, we should not have miscompile since later optimizations which look at the object's alignment will have the correct information. rdar://12713765 llvm-svn: 172027
* Fix a DAG combine bug visitBRCOND() is transforming br(xor(x, y)) to br(x != y).Evan Cheng2013-01-091-12/+18
| | | | | | | | | It cahced XOR's operands before calling visitXOR() but failed to update the operands when visitXOR changed the XOR node. rdar://12968664 llvm-svn: 171999
* Refactor to expose RTLIB calls to targets.Tim Northover2013-01-096-337/+367
| | | | | | | | | | fp128 is almost but not quite completely illegal as a type on AArch64. As a result it needs to have a register class (for argument passing mainly), but all operations need to be lowered to runtime calls. Currently there's no way for targets to do this (without duplicating code), as the relevant functions are hidden in SelectionDAG. This patch changes that. llvm-svn: 171971
* Add fp128 rtlib function names to LLVMTim Northover2013-01-082-18/+138
| | | | llvm-svn: 171867
* Sink a function that refers to the SelectionDAG into that library in theChandler Carruth2013-01-081-0/+21
| | | | | | | | | | | | | | one file where it is called as a static function. Nuke the declaration and the definition in lib/CodeGen, along with the include of SelectionDAG.h from this file. There is no dependency edge from lib/CodeGen to lib/CodeGen/SelectionDAG, so it isn't valid for a routine in lib/CodeGen to reference the DAG. There is a dependency from lib/CodeGen/SelectionDAG on lib/CodeGen. This breaks one violation of this layering. llvm-svn: 171842
* Sink AddrMode back into TargetLowering, removing one of the mostChandler Carruth2013-01-071-1/+1
| | | | | | | | | peculiar headers under include/llvm. This struct still doesn't make a lot of sense, but it makes more sense down in TargetLowering than it did before. llvm-svn: 171739
* Move TargetTransformInfo to live under the Analysis library. This noChandler Carruth2013-01-072-2/+2
| | | | | | | longer would violate any dependency layering and it is in fact an analysis. =] llvm-svn: 171686
* Switch TargetTransformInfo from an immutable analysis pass that requiresChandler Carruth2013-01-071-0/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | a TargetMachine to construct (and thus isn't always available), to an analysis group that supports layered implementations much like AliasAnalysis does. This is a pretty massive change, with a few parts that I was unable to easily separate (sorry), so I'll walk through it. The first step of this conversion was to make TargetTransformInfo an analysis group, and to sink the nonce implementations in ScalarTargetTransformInfo and VectorTargetTranformInfo into a NoTargetTransformInfo pass. This allows other passes to add a hard requirement on TTI, and assume they will always get at least on implementation. The TargetTransformInfo analysis group leverages the delegation chaining trick that AliasAnalysis uses, where the base class for the analysis group delegates to the previous analysis *pass*, allowing all but tho NoFoo analysis passes to only implement the parts of the interfaces they support. It also introduces a new trick where each pass in the group retains a pointer to the top-most pass that has been initialized. This allows passes to implement one API in terms of another API and benefit when some other pass above them in the stack has more precise results for the second API. The second step of this conversion is to create a pass that implements the TargetTransformInfo analysis using the target-independent abstractions in the code generator. This replaces the ScalarTargetTransformImpl and VectorTargetTransformImpl classes in lib/Target with a single pass in lib/CodeGen called BasicTargetTransformInfo. This class actually provides most of the TTI functionality, basing it upon the TargetLowering abstraction and other information in the target independent code generator. The third step of the conversion adds support to all TargetMachines to register custom analysis passes. This allows building those passes with access to TargetLowering or other target-specific classes, and it also allows each target to customize the set of analysis passes desired in the pass manager. The baseline LLVMTargetMachine implements this interface to add the BasicTTI pass to the pass manager, and all of the tools that want to support target-aware TTI passes call this routine on whatever target machine they end up with to add the appropriate passes. The fourth step of the conversion created target-specific TTI analysis passes for the X86 and ARM backends. These passes contain the custom logic that was previously in their extensions of the ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces. I separated them into their own file, as now all of the interface bits are private and they just expose a function to create the pass itself. Then I extended these target machines to set up a custom set of analysis passes, first adding BasicTTI as a fallback, and then adding their customized TTI implementations. The fourth step required logic that was shared between the target independent layer and the specific targets to move to a different interface, as they no longer derive from each other. As a consequence, a helper functions were added to TargetLowering representing the common logic needed both in the target implementation and the codegen implementation of the TTI pass. While technically this is the only change that could have been committed separately, it would have been a nightmare to extract. The final step of the conversion was just to delete all the old boilerplate. This got rid of the ScalarTargetTransformInfo and VectorTargetTransformInfo classes, all of the support in all of the targets for producing instances of them, and all of the support in the tools for manually constructing a pass based around them. Now that TTI is a relatively normal analysis group, two things become straightforward. First, we can sink it into lib/Analysis which is a more natural layer for it to live. Second, clients of this interface can depend on it *always* being available which will simplify their code and behavior. These (and other) simplifications will follow in subsequent commits, this one is clearly big enough. Finally, I'm very aware that much of the comments and documentation needs to be updated. As soon as I had this working, and plausibly well commented, I wanted to get it committed and in front of the build bots. I'll be doing a few passes over documentation later if it sticks. Commits to update DragonEgg and Clang will be made presently. llvm-svn: 171681
* Funnel the actual TargetTransformInfo pass from the SelectionDAGISelChandler Carruth2013-01-052-5/+9
| | | | | | | | | pass into the SelectionDAG itself rather than snooping on the implementation of that pass as exposed by the TargetMachine. This removes the last direct client of the ScalarTargetTransformInfo class outside of the TTI pass implementation. llvm-svn: 171625
* DAGCombiner: Avoid generating illegal vector INT_TO_FP nodesTom Stellard2013-01-021-4/+5
| | | | | | | | | | | | | | DAGCombiner::reduceBuildVecConvertToConvertBuildVec() was making two mistakes: 1. It was checking the legality of scalar INT_TO_FP nodes and then generating vector nodes. 2. It was passing the result value type to TargetLoweringInfo::getOperationAction() when it should have been passing the value type of the first operand. llvm-svn: 171420
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-0219-69/+69
| | | | | | | | | | | | | | | | | | | | | into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
* Resort the #include lines in include/... and lib/... with theChandler Carruth2013-01-021-1/+1
| | | | | | | | | | utils/sort_includes.py script. Most of these are updating the new R600 target and fixing up a few regressions that have creeped in since the last time I sorted the includes. llvm-svn: 171362
* Support ppcf128 in SelectionDAG::getConstantFPHal Finkel2012-12-301-1/+2
| | | | | | | | Fixes pr14751. Patch by Kai; Thanks! llvm-svn: 171261
* Remove the Function::getRetAttributes method in favor of using the ↵Bill Wendling2012-12-303-15/+15
| | | | | | AttributeSet accessor method. llvm-svn: 171256
* Remove Function::getParamAttributes and use the AttributeSet accessor ↵Bill Wendling2012-12-301-8/+8
| | | | | | methods instead. llvm-svn: 171255
* Remove the Function::getFnAttributes method in favor of using the AttributeSetBill Wendling2012-12-303-9/+11
| | | | | | | | | directly. This is in preparation for removing the use of the 'Attribute' class as a collection of attributes. That will shift to the AttributeSet class instead. llvm-svn: 171253
* Refactor DAGCombinerInfo. Change the different booleans that indicate if we ↵Nadav Rotem2012-12-272-3/+3
| | | | | | | | are before or after different runs of DAGCo, with the CombineLevel enum. Also, added a new API for checking if we are running before or after the LegalizeVectorOps phase. llvm-svn: 171142
* Use MachineInstrBuilder for PHI nodes in SelectionDAGISel.Jakob Stoklund Olesen2012-12-201-50/+25
| | | | llvm-svn: 170716
* Use MachineInstrBuilder in InstrEmitter.Jakob Stoklund Olesen2012-12-202-79/+73
| | | | | | | | | | | | This is supposed to be a mechanical change with no functional effects. InstrEmitter can generate all types of MachineOperands which revealed that MachineInstrBuilder was missing a few methods, added by this patch. Besides providing a context pointer to MI::addOperand(), MachineInstrBuilder seems like a better fit for this code. llvm-svn: 170712
* Do not introduce vector operations in functions marked with noimplicitfloat.Bob Wilson2012-12-201-2/+5
| | | | | | <rdar://problem/12879313> llvm-svn: 170630
* Change AsmOperandInfo::ConstraintVT to MVT, instead of EVT.Patrik Hagglund2012-12-192-8/+9
| | | | | | Accordingly, add MVT::getVT. llvm-svn: 170550
* Split the usage of 'EVT PartVT' into 'MVT PartVT' and 'EVT PartEVT'.Patrik Hagglund2012-12-191-38/+38
| | | | llvm-svn: 170540
* Change RegVT in BitTestBlock and RegsForValue, to contain MVTs,Patrik Hagglund2012-12-192-14/+13
| | | | | | instead of EVTs. llvm-svn: 170538
* Change TargetLowering::getTypeForExtArgOrReturn to take and returnPatrik Hagglund2012-12-191-1/+1
| | | | | | MVTs, instead of EVTs. llvm-svn: 170537
* Change a parameter of TargetLowering::getVectorTypeBreakdown to MVT,Patrik Hagglund2012-12-192-14/+19
| | | | | | from EVT. llvm-svn: 170536
* Change TargetLowering::RegisterTypeForVT to contain MVTs, instead ofPatrik Hagglund2012-12-195-18/+18
| | | | | | EVTs. llvm-svn: 170535
* Change TargetLowering::TransformToType to contain MVTs, instead ofPatrik Hagglund2012-12-191-4/+4
| | | | | | EVTs. llvm-svn: 170534
* Change TargetLowering::findRepresentativeClass to take an MVT, insteadPatrik Hagglund2012-12-191-2/+2
| | | | | | of EVT. llvm-svn: 170532
* Change TargetLowering::getTypeToPromoteTo to take and return MVTs,Patrik Hagglund2012-12-192-9/+9
| | | | | | instead of EVTs. llvm-svn: 170529
* Change TargetLowering::isCondCodeLegal to take an MVT, instead of EVT.Patrik Hagglund2012-12-192-12/+15
| | | | llvm-svn: 170524
* Change TargetLowering::getCondCodeAction to take an MVT, instead ofPatrik Hagglund2012-12-192-4/+4
| | | | | | EVT. llvm-svn: 170522
* Change TargetLowering::getTruncStoreAction to take MVTs, instead of EVTs.Patrik Hagglund2012-12-192-3/+4
| | | | llvm-svn: 170510
* Optimized load + SIGN_EXTEND patterns in the X86 backend.Elena Demikhovsky2012-12-191-0/+1
| | | | llvm-svn: 170506
* After reducing the size of an operation in the DAG we zero-extend the reducedNadav Rotem2012-12-191-2/+5
| | | | | | | | bitwidth op back to the original size. If we reduce ANDs then this can cause an endless loop. This patch changes the ZEXT to ANY_EXTEND if the demanded bits are equal or smaller than the size of the reduced operation. llvm-svn: 170505
* Rename the 'Attributes' class to 'Attribute'. It's going to represent a ↵Bill Wendling2012-12-193-27/+27
| | | | | | single attribute in the future. llvm-svn: 170502
* Remove more of 'else's after 'returns'. No functional change.Craig Topper2012-12-191-6/+6
| | | | llvm-svn: 170497
* Remove a bunch of 'else's after 'returns'Craig Topper2012-12-191-18/+18
| | | | llvm-svn: 170496
* Teach SimplifySetCC that comparing AssertZext i1 against a constant 1 can be ↵Craig Topper2012-12-191-3/+9
| | | | | | rewritten as a compare against a constant 0 with the opposite condition. llvm-svn: 170495
* Check multiple register classes for inline asm tied registersHal Finkel2012-12-181-3/+16
| | | | | | | | | | | | | | | | | | A register can be associated with several distinct register classes. For example, on PPC, the floating point registers are each associated with both F4RC (which holds f32) and F8RC (which holds f64). As a result, this code would fail when provided with a floating point register and an f64 operand because it would happen to find the register in the F4RC class first and return that. From the F4RC class, SDAG would extract f32 as the register type and then assert because of the invalid implied conversion between the f64 value and the f32 register. Instead, search all register classes. If a register class containing the the requested register has the requested type, then return that register class. Otherwise, as before, return the first register class found that contains the requested register. llvm-svn: 170436
* Revert/correct some FastISel changes in r170104 (EVT->MVT forPatrik Hagglund2012-12-171-5/+6
| | | | | | | | | TargetLowering::getRegClassFor). Some isSimple() guards were missing, or getSimpleVT() were hoisted too far, resulting in asserts on valid LLVM assembly input. llvm-svn: 170336
* Change TargetLowering::getLoadExtAction to take an MVT, instead ofPatrik Hagglund2012-12-141-1/+1
| | | | | | EVT. llvm-svn: 170183
* Change TargetLowering::setTypeAction to take an MVT, instead fo EVT.Patrik Hagglund2012-12-131-1/+1
| | | | llvm-svn: 170148
* Change TargetLowering::getRepRegClassFor to take an MVT, instead ofPatrik Hagglund2012-12-133-11/+11
| | | | | | | | EVT. Accordingly, change RegDefIter to contain MVTs instead of EVTs. llvm-svn: 170140
* Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.Patrik Hagglund2012-12-136-30/+30
| | | | | | | | | | | | Accordingly, add helper funtions getSimpleValueType (in parallel to getValueType) in SDValue, SDNode, and TargetLowering. This is the first, in a series of patches. This is the second attempt. In the first attempt (r169837), a few getSimpleVT() were hoisted too far, detected by bootstrap failures. llvm-svn: 170104
* Fix a bug in DAGCombiner::MatchBSwapHWord. Make sure the node has operands ↵Evan Cheng2012-12-131-1/+2
| | | | | | before referencing them. rdar://12868039 llvm-svn: 170078
* Fix a logic bug in inline expansion of memcpy / memset with an overlappingEvan Cheng2012-12-121-4/+5
| | | | | | | load / store pair. It's not legal to use a wider load than the size of the remaining bytes if it's the first pair of load / store. llvm-svn: 170018
* Sorry about the churn. One more change to getOptimalMemOpType() hook. Did IEvan Cheng2012-12-121-6/+7
| | | | | | | | | | | | mention the inline memcpy / memset expansion code is a mess? This patch split the ZeroOrLdSrc argument into two: IsMemset and ZeroMemset. The first indicates whether it is expanding a memset or a memcpy / memmove. The later is whether the memset is a memset of zero. It's totally possible (likely even) that targets may want to do different things for memcpy and memset of zero. llvm-svn: 169959
* - Rename isLegalMemOpType to isSafeMemOpType. "Legal" is a very overloade term.Evan Cheng2012-12-121-5/+5
| | | | | | | | | Also added more comments to explain why it is generally ok to return true. - Rename getOptimalMemOpType argument IsZeroVal to ZeroOrLdSrc. It's meant to be true for loaded source (memcpy) or zero constants (memset). The poor name choice is probably some kind of legacy issue. llvm-svn: 169954
* DAGCombine: clamp hi bit in APInt::getBitsSet to avoid assertionManman Ren2012-12-121-1/+2
| | | | | | rdar://12838504 llvm-svn: 169951
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