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* remove dead makefile flags.Chris Lattner2009-06-241-2/+0
| | | | llvm-svn: 74065
* Fix memcpy expansion so it won't generate invalidDale Johannesen2009-06-221-6/+25
| | | | | | | types for the target (I think). This was breaking the PPC32 calling sequence. llvm-svn: 73900
* mv CodeGen/DebugLoc.h Support/DebugLoc.hDevang Patel2009-06-191-1/+0
| | | | llvm-svn: 73786
* Minor cleanup; fixes review comments for a previous patch. Sorry for Eli Friedman2009-06-191-4/+3
| | | | | | taking so long to get to this! llvm-svn: 73757
* Fixed names of libcalls checked in r73480.Sanjiv Gupta2009-06-161-8/+4
| | | | llvm-svn: 73483
* Added required libcalls for PIC16 (mostly floating points to integer casting ↵Sanjiv Gupta2009-06-161-0/+16
| | | | | | operations). llvm-svn: 73480
* Add some generic expansion logic for SMULO and UMULO. Fixes UMULO Eli Friedman2009-06-161-0/+47
| | | | | | | | support for x86, and UMULO/SMULO for many architectures, including PPC (PR4201), ARM, and Cell. The resulting expansion isn't perfect, but it's not bad. llvm-svn: 73477
* Change this from an assert to a cerr+exit, since it's diagnosing anDan Gohman2009-06-151-2/+6
| | | | | | unsupported inline asm construct, rather than verifying a code invariant. llvm-svn: 73435
* Gracefully handle imbalanced inline function begin and end markers.Devang Patel2009-06-151-1/+1
| | | | llvm-svn: 73426
* CheckTailCallReturnConstraints is missing a check on theArnold Schwaighofer2009-06-151-1/+5
| | | | | | | | | incomming chain of the RETURN node. The incomming chain must be the outgoing chain of the CALL node. This causes the backend to identify tail calls that are not tail calls. This patch fixes this. llvm-svn: 73387
* Tweak the expansion code for BIT_CONVERT to generate better code Eli Friedman2009-06-071-0/+20
| | | | | | converting from an MMX vector to an i64. llvm-svn: 73024
* Slightly generalize the code that handles shuffles of consecutive loads Eli Friedman2009-06-071-78/+37
| | | | | | | | | | | on x86 to handle more cases. Fix a bug in said code that would cause it to read past the end of an object. Rewrite the code in SelectionDAGLegalize::ExpandBUILD_VECTOR to be a bit more general. Remove PerformBuildVectorCombine, which is no longer necessary with these changes. In addition to simplifying the code, with this change, we can now catch a few more cases of consecutive loads. llvm-svn: 73012
* Fix the expansion for CONCAT_VECTORS so that it doesn't create illegal Eli Friedman2009-06-061-17/+1
| | | | | | types. llvm-svn: 72993
* Factor out a couple of helpers.Eli Friedman2009-06-061-78/+101
| | | | llvm-svn: 72992
* Make SINT_TO_FP/UINT_TO_FP vector legalization queries query on the Eli Friedman2009-06-061-3/+7
| | | | | | | integer type to be consistent with normal operation legalization. No visible change because nothing is actually using this at the moment. llvm-svn: 72980
* Add new function attribute - noimplicitfloatDevang Patel2009-06-051-1/+1
| | | | | | | Update code generator to use this attribute and remove NoImplicitFloat target option. Update llc to set this attribute when -no-implicit-float command line option is used. llvm-svn: 72959
* Adapt the x86 build_vector dagcombine to the current state of the legalizer.Nate Begeman2009-06-052-16/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | build vectors with i64 elements will only appear on 32b x86 before legalize. Since vector widening occurs during legalize, and produces i64 build_vector elements, the dag combiner is never run on these before legalize splits them into 32b elements. Teach the build_vector dag combine in x86 back end to recognize consecutive loads producing the low part of the vector. Convert the two uses of TLI's consecutive load recognizer to pass LoadSDNodes since that was required implicitly. Add a testcase for the transform. Old: subl $28, %esp movl 32(%esp), %eax movl 4(%eax), %ecx movl %ecx, 4(%esp) movl (%eax), %eax movl %eax, (%esp) movaps (%esp), %xmm0 pmovzxwd %xmm0, %xmm0 movl 36(%esp), %eax movaps %xmm0, (%eax) addl $28, %esp ret New: movl 4(%esp), %eax pmovzxwd (%eax), %xmm0 movl 8(%esp), %eax movaps %xmm0, (%eax) ret llvm-svn: 72957
* Allow libcalls for i16 sdiv/udiv/rem operations.Sanjiv Gupta2009-06-051-4/+12
| | | | llvm-svn: 72941
* Split the Add, Sub, and Mul instruction opcodes into separateDan Gohman2009-06-043-47/+32
| | | | | | | | | | | | | | | integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897
* Fix FP_TO_UINT->i32 on ppc32 -mcpu=g5. This wasDale Johannesen2009-06-041-6/+5
| | | | | | | | | | | | | | using Promote which won't work because i64 isn't a legal type. It's easy enough to use Custom, but then we have the problem that when the type legalizer is promoting FP_TO_UINT->i16, it has no way of telling it should prefer FP_TO_SINT->i32 to FP_TO_UINT->i32. I have uncomfortably hacked this by making the type legalizer choose FP_TO_SINT when both are Custom. This fixes several regressions in the testsuite. llvm-svn: 72891
* Don't do the X * 0.0 -> 0.0 transformation in instcombine, becauseDan Gohman2009-06-042-5/+11
| | | | | | | | instcombine doesn't know when it's safe. To partially compensate for this, introduce new code to do this transformation in dagcombine, which can use UnsafeFPMath. llvm-svn: 72872
* Fix comments.Dan Gohman2009-06-041-2/+2
| | | | llvm-svn: 72870
* Revert 72707 and 72709, for the moment.Dale Johannesen2009-06-025-68/+19
| | | | llvm-svn: 72712
* Make the implicit inputs and outputs of target-independentDale Johannesen2009-06-015-19/+68
| | | | | | | | | | | | | | | | | | | | | | | | ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to) instead of MVT::Flag. Remove CARRY_FALSE in favor of 0; adjust all target-independent code to use this format. Most targets will still produce a Flag-setting target-dependent version when selection is done. X86 is converted to use i32 instead, which means TableGen needs to produce different code in xxxGenDAGISel.inc. This keys off the new supportsHasI1 bit in xxxInstrInfo, currently set only for X86; in principle this is temporary and should go away when all other targets have been converted. All relevant X86 instruction patterns are modified to represent setting and using EFLAGS explicitly. The same can be done on other targets. The immediate behavior change is that an ADC/ADD pair are no longer tightly coupled in the X86 scheduler; they can be separated by instructions that don't clobber the flags (MOV). I will soon add some peephole optimizations based on using other instructions that set the flags to feed into ADC. llvm-svn: 72707
* Rename CustomLowerResults to CustomLowerNode, sinceDuncan Sands2009-05-314-9/+8
| | | | | | | it is used both when a result is illegal and when an operand is illegal. llvm-svn: 72658
* Untabification.Bill Wendling2009-05-301-4/+4
| | | | llvm-svn: 72604
* Do not try to create a MVT type of width 0.Evan Cheng2009-05-281-0/+2
| | | | llvm-svn: 72557
* Re-commit r72514 and r72516 with a fixed version of BR_CC lowering. Eli Friedman2009-05-281-87/+38
| | | | | | | This patch removes some special cases for opcodes and does a bit of cleanup. llvm-svn: 72536
* Incorporate patch feedbacks.Evan Cheng2009-05-281-11/+17
| | | | llvm-svn: 72533
* Temporarily revert r72514 (and dependent patch r72516). It was causing thisBill Wendling2009-05-281-36/+87
| | | | | | | | | | | | failure during llvm-gcc bootstrap: Assertion failed: (!Tmp2.getNode() && "Can't legalize BR_CC with legal condition!"), function ExpandNode, file /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore.roots/llvmCore~obj/src/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp, line 2923. /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/libgcc2.c:1727: internal compiler error: Abort trap Please submit a full bug report, with preprocessed source if appropriate. See <URL:http://developer.apple.com/bugreporter> for instructions. llvm-svn: 72530
* Remove a couple of useless functions.Eli Friedman2009-05-281-34/+6
| | | | llvm-svn: 72516
* Remove special cases for more opcodes.Eli Friedman2009-05-281-65/+42
| | | | | | | | | This is basically the end of this series of patches for LegalizeDAG; the remaining special cases can't be removed without more infrastructure work. There's a FIXME for each relevant opcode near the beginning of SelectionDAGLegalize::LegalizeOp. llvm-svn: 72514
* Remove special case for SETCC opcode; add some comments explaining why Eli Friedman2009-05-281-73/+63
| | | | | | some special cases are necessary. llvm-svn: 72511
* Some minor cleanups.Eli Friedman2009-05-281-54/+30
| | | | llvm-svn: 72509
* Added optimization that narrow load / op / store and the 'op' is a bit ↵Evan Cheng2009-05-281-1/+93
| | | | | | | | | | | | | twiddling instruction and its second operand is an immediate. If bits that are touched by 'op' can be done with a narrower instruction, reduce the width of the load and store as well. This happens a lot with bitfield manipulation code. e.g. orl $65536, 8(%rax) => orb $1, 10(%rax) Since narrowing is not always a win, e.g. i32 -> i16 is a loss on x86, dag combiner consults with the target before performing the optimization. llvm-svn: 72507
* Minor cleanups; add a better explanation for the issue with Eli Friedman2009-05-271-23/+10
| | | | | | BUILD_VECTOR. llvm-svn: 72469
* Remove more special cases for opcodes.Eli Friedman2009-05-271-310/+201
| | | | llvm-svn: 72468
* Remove special cases for more opcodes.Eli Friedman2009-05-272-207/+122
| | | | llvm-svn: 72467
* Removing more special cases from LegalizeDAG.Eli Friedman2009-05-271-191/+78
| | | | llvm-svn: 72465
* Eliminate more special cases for opcodes.Eli Friedman2009-05-271-192/+105
| | | | llvm-svn: 72464
* Remove more special cases from LegalizeDAG.Eli Friedman2009-05-271-210/+145
| | | | llvm-svn: 72456
* Remove unused argument.Eli Friedman2009-05-271-11/+6
| | | | llvm-svn: 72455
* Remove more opcode special cases.Eli Friedman2009-05-271-159/+70
| | | | llvm-svn: 72454
* Start of refactoring LegalizeDAG so that we don't need specialized Eli Friedman2009-05-271-1185/+363
| | | | | | handling for every single opcode. llvm-svn: 72447
* Delete a bunch of dead code from LegalizeDAG.Eli Friedman2009-05-261-3667/+29
| | | | llvm-svn: 72414
* Add a comment which should hopefully make the purpose of this method a Eli Friedman2009-05-241-0/+3
| | | | | | bit clearer. llvm-svn: 72374
* Minor improvement to FCOPYSIGN to use BIT_CONVERT in cases where the Eli Friedman2009-05-241-10/+24
| | | | | | corresponding integer type is legal. llvm-svn: 72373
* Rewrite ISD::FCOPYSIGN lowering to never use i64. Not really ideal, but Eli Friedman2009-05-241-30/+21
| | | | | | it's late, and I don't have any better ideas at the moment. Fixes PR4257. llvm-svn: 72363
* Update for CMakeLists; untested, so tell me if there are issues.Eli Friedman2009-05-241-0/+1
| | | | llvm-svn: 72360
* Remove checks of getTypeAction from LegalizeOp; we already assert that Eli Friedman2009-05-241-503/+105
| | | | | | | all results and all operands are legal, so this change shouldn't affect behavior at all. llvm-svn: 72359
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