summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/SelectionDAG
Commit message (Collapse)AuthorAgeFilesLines
* Add a new target hook "predictableSelectIsExpensive".Benjamin Kramer2012-05-051-0/+1
| | | | | | | | | | | This will be used to determine whether it's profitable to turn a select into a branch when the branch is likely to be predicted. Currently enabled for everything but Atom on X86 and Cortex-A9 devices on ARM. I'm not entirely happy with the name of this flag, suggestions welcome ;) llvm-svn: 156233
* Make sure findRepresentativeClass picks the widest super-register.Jakob Stoklund Olesen2012-05-041-6/+10
| | | | | | | | We want the representative register class to contain the largest super-registers available. This makes the function less sensitive to the register class numbering. llvm-svn: 156220
* Use SuperRegClassIterator for findRepresentativeClass().Jakob Stoklund Olesen2012-05-041-26/+15
| | | | | | | | The masks returned by SuperRegClassIterator are computed automatically by TableGen. This is better than depending on the manually specified SuperRegClasses. llvm-svn: 156147
* Added TargetRegisterInfo::getAllocatableClass.Andrew Trick2012-05-031-6/+10
| | | | | | | | | | The ensures that virtual registers always belong to an allocatable class. If your target attempts to create a vreg for an operand that has no allocatable register subclass, you will crash quickly. This ensures that targets define register classes as intended. llvm-svn: 156046
* Teach DAGCombine the same multiply-by-1.0 folding trick when doing FMAs, ↵Owen Anderson2012-05-021-0/+18
| | | | | | just like it now knows for FMULs. llvm-svn: 156029
* Teach DAG combine that multiplication by 1.0 can always be constant folded.Owen Anderson2012-05-021-0/+3
| | | | llvm-svn: 156023
* Use dyn_cast instead of checking opcode and cast.Jakub Staszak2012-05-011-2/+1
| | | | llvm-svn: 155957
* Strip the pointer casts off of allocas so that the selection DAG can find them.Bill Wendling2012-05-011-1/+1
| | | | | | PR10799 llvm-svn: 155954
* Add some constantness. No functionality change.Jakub Staszak2012-04-301-9/+9
| | | | llvm-svn: 155859
* Reapply 155668: Fix the SD scheduler to avoid gluing the same node twice.Andrew Trick2012-04-281-26/+58
| | | | | | | | | | This time, also fix the caller of AddGlue to properly handle incomplete chains. AddGlue had failure modes, but shamefully hid them from its caller. It's luck ran out. Fixes rdar://11314175: BuildSchedUnits assert. llvm-svn: 155749
* Temporarily revert r155668: Fix the SD scheduler to avoid gluing.Andrew Trick2012-04-271-4/+2
| | | | | | This definitely caused regression with ARM -mno-thumb. llvm-svn: 155743
* Fix the SD scheduler to avoid gluing the same node twice.Andrew Trick2012-04-261-3/+5
| | | | | | | | | | | DAGCombine strangeness may result in multiple loads from the same offset. They both may try to glue themselves to another load. We could insist that the redundant loads glue themselves to each other, but the beter fix is to bail out from bad gluing at the time we detect it. Fixes rdar://11314175: BuildSchedUnits assert. llvm-svn: 155668
* ZERO_EXTEND/SIGN_EXTEND/TRUNCATE optimization for AVX2Elena Demikhovsky2012-04-221-0/+2
| | | | llvm-svn: 155309
* Teach getVectorTypeBreakdown about promotion of vectors in addition to ↵Nadav Rotem2012-04-211-3/+6
| | | | | | widening of vectors. llvm-svn: 155296
* Fix PR12599.Jakob Stoklund Olesen2012-04-201-1/+6
| | | | | | | | The X86 target is editing the selection DAG while isel is selecting nodes following a topological ordering. When the DAG hacking triggers CSE, nodes can be deleted and bad things happen. llvm-svn: 155257
* Make ISelPosition a local variable.Jakob Stoklund Olesen2012-04-201-8/+25
| | | | | | | | | Now that multiple DAGUpdateListeners can be active at the same time, ISelPosition can become a local variable in DoInstructionSelection. We simply register an ISelUpdater with CurDAG while ISelPosition exists. llvm-svn: 155249
* Register DAGUpdateListeners with SelectionDAG.Jakob Stoklund Olesen2012-04-206-119/+87
| | | | | | | | | | | | | | | Instead of passing listener pointers to RAUW, let SelectionDAG itself keep a linked list of interested listeners. This makes it possible to have multiple listeners active at once, like RAUWUpdateListener was already doing. It also makes it possible to register listeners up the call stack without controlling all RAUW calls below. DAGUpdateListener uses an RAII pattern to add itself to the SelectionDAG list of active listeners. llvm-svn: 155248
* Fixes a problem in instruction selection with testing whether or not the Joel Jones2012-04-171-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | transformation: (X op C1) ^ C2 --> (X op C1) & ~C2 iff (C1&C2) == C2 should be done. This change has been tested: Using a debug+asserts build: on the specific test case that brought this bug to light make check-all lnt nt using this clang to build a release version of clang Using the release+asserts clang-with-clang build: on the specific test case that brought this bug to light make check-all lnt nt Checking in because Evan wants it checked in. Test case forthcoming after scrubbing. llvm-svn: 154955
* Remove dead SD nodes after the combining pass. Fixes PR12201.Hal Finkel2012-04-161-0/+1
| | | | llvm-svn: 154786
* When emulating vselect using OR/AND/XOR make sure to bitcast the result back ↵Nadav Rotem2012-04-151-1/+2
| | | | | | to the original type. llvm-svn: 154764
* Reapply 154397. Original message:Nadav Rotem2012-04-111-11/+18
| | | | | | | | Fix a dagcombine optimization which assumes that the vsetcc result type is always of the same size as the compared values. This is ture for SSE/AVX/NEON but not for all targets. llvm-svn: 154490
* Fix an overly indented line. Remove an 'else' after an 'if' that returns.Craig Topper2012-04-111-4/+3
| | | | llvm-svn: 154479
* Inline implVisitAluOverflow by introducing a nested switch to convert the ↵Craig Topper2012-04-112-20/+18
| | | | | | intrinsic to an nodetype. llvm-svn: 154478
* Optimize code a bit by calling push_back only once in some loops. Reduces ↵Craig Topper2012-04-111-26/+24
| | | | | | compiled code size a bit. llvm-svn: 154473
* Move the constant-folding support for FP_ROUND in SelectionDAG from the ↵Owen Anderson2012-04-101-1/+10
| | | | | | | | one-operand version of getNode() to the two-operand version, since it became a two-operand node at sound point. Zap a testcase that this allows us to completely fold away. llvm-svn: 154447
* Add a comment noting that the fdiv -> fmul conversion won't generateDuncan Sands2012-04-101-3/+3
| | | | | | multiplication by a denormal, and some tests checking that. llvm-svn: 154431
* To ensure that we have more accurate line information for a blockEric Christopher2012-04-101-2/+5
| | | | | | | | | don't elide the branch instruction if it's the only one in the block, otherwise it's ok. PR9796 and rdar://11215207 llvm-svn: 154417
* Revert r154397, which was causing make check failures on the buildbots.Owen Anderson2012-04-101-13/+6
| | | | llvm-svn: 154414
* Fix a dagcombine optimization which assumes that the vsetcc result type is ↵Nadav Rotem2012-04-101-6/+13
| | | | | | | | | always of the same size as the compared values. This is ture for SSE/AVX/NEON but not for all targets. llvm-svn: 154397
* Transform div to mul with reciprocal only when fp imm is legal.Anton Korobeynikov2012-04-101-2/+9
| | | | | | This fixes PR12516 and uncovers one weird problem in legalize (workarounded) llvm-svn: 154394
* Make the code slightly more palatable.Evan Cheng2012-04-101-1/+5
| | | | llvm-svn: 154378
* Fix a long standing tail call optimization bug. When a libcall is emittedEvan Cheng2012-04-101-7/+8
| | | | | | | | | | | | | legalizer always use the DAG entry node. This is wrong when the libcall is emitted as a tail call since it effectively folds the return node. If the return node's input chain is not the entry (i.e. call, load, or store) use that as the tail call input chain. PR12419 rdar://9770785 rdar://11195178 llvm-svn: 154370
* Don't try to zExt just to check if an integer constant is zero, it mightRafael Espindola2012-04-101-2/+2
| | | | | | not fit in a i64. llvm-svn: 154364
* Have TargetLowering::getPICJumpTableRelocBase return a node that points to theAkira Hatanaka2012-04-091-1/+5
| | | | | | GOT if jump table uses 64-bit gp-relative relocation. llvm-svn: 154341
* Pattern match a setcc of boolean value with 0 as a truncate.Rafael Espindola2012-04-091-9/+48
| | | | llvm-svn: 154322
* Remove unnecessary type check when combining and/or/xor of swizzles. Move ↵Craig Topper2012-04-091-13/+12
| | | | | | some checks to allow better early out. llvm-svn: 154309
* Remove unnecessary 'else' on an 'if' that always returnsCraig Topper2012-04-091-1/+2
| | | | llvm-svn: 154308
* Optimize code slightly. No functionality change.Craig Topper2012-04-091-6/+7
| | | | llvm-svn: 154307
* Replace some explicit checks with asserts for conditions that should never ↵Craig Topper2012-04-091-14/+7
| | | | | | happen. llvm-svn: 154305
* Optimize code a bit. No functional change intended.Craig Topper2012-04-081-9/+9
| | | | llvm-svn: 154299
* Silence sign-compare warning.Benjamin Kramer2012-04-081-1/+1
| | | | llvm-svn: 154297
* Only have codegen turn fdiv by a constant into fmul by the reciprocalDuncan Sands2012-04-081-5/+3
| | | | | | | | when -ffast-math, i.e. don't just always do it if the reciprocal can be formed exactly. There is already an IR level transform that does that, and it does it more carefully. llvm-svn: 154296
* Simplify code that tries to do vector extracts for shuffles when the mask ↵Craig Topper2012-04-081-12/+8
| | | | | | width and the input vector widths don't match. No need to check the min and max are in range before calculating the start index. The range check after having the start index is sufficient. Also no need to check for an extract from the beginning differently. llvm-svn: 154295
* Move the TLSModel information into the TargetMachine rather than hidingChandler Carruth2012-04-081-22/+0
| | | | | | | | in TargetLowering. There was already a FIXME about this location being odd. The interface is simplified as a consequence. This will also make it easier to change TLS models when compiling with PIE. llvm-svn: 154292
* Turn avx2 vinserti128 intrinsic calls into INSERT_SUBVECTOR DAG nodes and ↵Craig Topper2012-04-071-1/+2
| | | | | | remove patterns for selecting the intrinsic. Similar was already done for avx1. llvm-svn: 154272
* Remove 'else' after 'if' that ends in return.Craig Topper2012-04-071-1/+1
| | | | llvm-svn: 154267
* 1. Remove the part of r153848 which optimizes shuffle-of-shuffle into a newNadav Rotem2012-04-071-12/+14
| | | | | | | | | | shuffle node because it could introduce new shuffle nodes that were not supported efficiently by the target. 2. Add a more restrictive shuffle-of-shuffle optimization for cases where the second shuffle reverses the transformation of the first shuffle. llvm-svn: 154266
* Convert floating point division by a constant into multiplication by theDuncan Sands2012-04-071-0/+13
| | | | | | | | reciprocal if converting to the reciprocal is exact. Do it even if inexact if -ffast-math. This substantially speeds up ac.f90 from the polyhedron benchmarks. llvm-svn: 154265
* Don't break the IV update in TLI::SimplifySetCC().Jakob Stoklund Olesen2012-04-051-15/+27
| | | | | | | | | | | | | | | | | | | LSR always tries to make the ICmp in the loop latch use the incremented induction variable. This allows the induction variable to be kept in a single register. When the induction variable limit is equal to the stride, SimplifySetCC() would break LSR's hard work by transforming: (icmp (add iv, stride), stride) --> (cmp iv, 0) This forced us to use lea for the IC update, preventing the simpler incl+cmp. <rdar://problem/7643606> <rdar://problem/11184260> llvm-svn: 154119
* Treat f16 the same as f80/f128 for the purposes of generating constants ↵Owen Anderson2012-04-051-1/+2
| | | | | | during instruction selection. llvm-svn: 154113
OpenPOWER on IntegriCloud