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* Cleanup: DAG building is specific to either SD or MI scheduling. Not part of ↵Andrew Trick2012-03-071-1/+1
| | | | | | the target interface. llvm-svn: 152174
* Extend r148086 to check for [r +/- reg] address mode. This fixes queens ↵Evan Cheng2012-03-061-4/+7
| | | | | | performance regression (due to increased register pressure from overly aggressive pre-inc formation). llvm-svn: 152162
* Make it possible for a target to mark FSUB as Expand. This requires ↵Owen Anderson2012-03-062-16/+39
| | | | | | providing a default expansion (FADD+FNEG), and teaching DAGCombine not to form FSUBs post-legalize if they are not legal. llvm-svn: 152079
* Fix warnings about adding a bool to a string.Bill Wendling2012-03-051-2/+2
| | | | | | Patch by Sean Silva! llvm-svn: 152042
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-042-2/+2
| | | | llvm-svn: 152001
* Fix a codegen fault in which log2 or exp2 could be dead-code eliminated even ↵James Molloy2012-03-011-2/+4
| | | | | | | | though they could have sideeffects. Only allow log2/exp2 to be converted to an intrinsic if they are declared "readnone". llvm-svn: 151807
* LegalizeIntegerTypes: Reorder operations in the "big shift by small amount" ↵Benjamin Kramer2012-02-291-4/+4
| | | | | | optimization, making the lives of later passes easier. llvm-svn: 151722
* Re-commit r151623 with fix. Only issue special no-return calls if it's a ↵Evan Cheng2012-02-285-20/+29
| | | | | | direct call. llvm-svn: 151645
* Fix off-by one in comment.Benjamin Kramer2012-02-281-1/+1
| | | | llvm-svn: 151644
* LegalizeIntegerTypes: Reenable the large shift with small amount optimization.Benjamin Kramer2012-02-281-11/+21
| | | | | | | | | | | | | To avoid problems with zero shifts when getting the bits that move between words we use a trick: first shift the by amount-1, then do another shift by one. When amount is 0 (and size 32) we first shift by 31, then by one, instead of by 32. Also fix a latent bug that emitted the low and high words in the wrong order when shifting right. Fixes PR12113. llvm-svn: 151637
* Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack ↵Daniel Dunbar2012-02-285-29/+20
| | | | | | prediction. ...", it is breaking the Clang build during the Compiler-RT part. llvm-svn: 151630
* Code cleanup following CR by Duncan.Nadav Rotem2012-02-281-5/+3
| | | | llvm-svn: 151627
* Fix a bug in the code that builds SDNodes from vector GEPs.Nadav Rotem2012-02-281-0/+4
| | | | | | | | | | | When the GEP index is a vector of pointers, the code that calculated the size of the element started from the vector type, and not the contained pointer type. As a result, instead of looking at the data element pointed by the vector, this code used the size of the vector. This works for 32bit members (on 32bit systems), but not for other types. Added code to peel the vector type and added a test. llvm-svn: 151626
* Some ARM implementaions, e.g. A-series, does return stack prediction. That is,Evan Cheng2012-02-285-20/+29
| | | | | | | | | | | | | | | | | the processor keeps a return addresses stack (RAS) which stores the address and the instruction execution state of the instruction after a function-call type branch instruction. Calling a "noreturn" function with normal call instructions (e.g. bl) can corrupt RAS and causes 100% return misprediction so LLVM should use a unconditional branch instead. i.e. mov lr, pc b _foo The "mov lr, pc" is issued in order to get proper backtrace. rdar://8979299 llvm-svn: 151623
* Don't crash when a glue node contains an internal CopyToRegHal Finkel2012-02-241-0/+3
| | | | | | | This is necessary to support the existing ppc lowering code for indirect calls. Fixes PR12071. llvm-svn: 151373
* SDAGBuilder: Remove register sets that were never read and prune dead code ↵Benjamin Kramer2012-02-241-63/+3
| | | | | | surrounding it. llvm-svn: 151364
* Turn avx insert intrinsic calls into INSERT_SUBVECTOR DAG nodes and remove ↵Pete Cooper2012-02-241-0/+15
| | | | | | duplicate patterns for selecting the intrinsics llvm-svn: 151342
* If the Address of a variable is an argument then treat the entireEric Christopher2012-02-241-3/+7
| | | | | | | | | | | variable declaration as an argument because we want that address anyhow for our debug information. This seems to fix rdar://9965111, at least we have more debug information than before and from reading the assembly it appears to be the correct location. llvm-svn: 151335
* Tabs, formatting and long lines oh my!Eric Christopher2012-02-241-4/+6
| | | | llvm-svn: 151334
* Allow an integer to be converted into an MMX type when it's used in an inlineBill Wendling2012-02-231-2/+8
| | | | | | | asm. <rdar://problem/10106006> llvm-svn: 151303
* More newline cleanups.Eric Christopher2012-02-232-4/+4
| | | | llvm-svn: 151235
* Add some handy-dandy newlines.Eric Christopher2012-02-231-2/+2
| | | | llvm-svn: 151234
* Properly emit _fltused with FastISel. Refactor to share code with SDAG.Michael J. Spencer2012-02-223-16/+29
| | | | | | Patch by Joe Groff! llvm-svn: 151183
* Make all pointers to TargetRegisterClass const since they are all pointers ↵Craig Topper2012-02-221-2/+2
| | | | | | to static data that should not be modified. llvm-svn: 151134
* Teach the DAGCombiner that certain loadext nodes followed by ANDs can be ↵James Molloy2012-02-201-0/+82
| | | | | | converted to zeroexts. llvm-svn: 150957
* Ignore the lifetime intrinsics in fast-isel.Eric Christopher2012-02-171-0/+4
| | | | llvm-svn: 150848
* Remove extraneous #include and spelling mistake introduced in r150669.James Molloy2012-02-161-2/+1
| | | | llvm-svn: 150670
* Modify the algorithm when traversing the DAGCombiner's worklist to be O(log ↵James Molloy2012-02-161-13/+36
| | | | | | N) for all operations. This fixes a horrible worst case with lots of nodes where 99% of the time was being spent in std::remove. llvm-svn: 150669
* Added hook to let targets custom lower splitting of illegal vectorsPete Cooper2012-02-151-0/+4
| | | | llvm-svn: 150550
* Fix PR12000. Some vector operations may use scalar operands with typesNadav Rotem2012-02-141-1/+5
| | | | | | | | that are greater than the vector element type. For example BUILD_VECTOR of type <1 x i1> with a constant i8 operand. This patch fixes the assertion. llvm-svn: 150477
* Rename getExceptionAddressRegister() to getExceptionPointerRegister() for ↵Lang Hames2012-02-143-3/+3
| | | | | | consistency with setExceptionPointerRegister(...). llvm-svn: 150460
* Don't reserve the R0 and R1 registers here. We don't use these registers, andBill Wendling2012-02-131-0/+6
| | | | | | | marking them as "live-in" into a BB ruins some invariants that the back-end tries to maintain. llvm-svn: 150437
* Add register mask support to ScheduleDAGRRList.Jakob Stoklund Olesen2012-02-131-11/+49
| | | | | | | | | The scheduler will sometimes check the implicit-def list on instructions to properly handle pre-colored DAG edges. Also check any register mask operands for physreg clobbers. llvm-svn: 150428
* Fix a bug in DAGCombine for the optimization of BUILD_VECTOR. We cant ↵Nadav Rotem2012-02-131-2/+6
| | | | | | generate a shuffle node from two vectors of different types. llvm-svn: 150383
* This patch addresses the problem of poor code generation for the zextNadav Rotem2012-02-121-14/+29
| | | | | | | | | | | | | | | | | | | v8i8 -> v8i32 on AVX machines. The codegen often scalarizes ANY_EXTEND nodes. The DAGCombiner has two optimizations that can mitigate the problem. First, if all of the operands of a BUILD_VECTOR node are extracted from an ZEXT/ANYEXT nodes, then it is possible to create a new simplified BUILD_VECTOR which uses UNDEFS/ZERO values to eliminate the scalar ZEXT/ANYEXT nodes. Second, another dag combine optimization lowers BUILD_VECTOR into a shuffle vector instruction. In the case of zext v8i8->v8i32 on AVX, a value in an XMM register is to be shuffled into a wide YMM register. This patch modifes the second optimization and allows the creation of shuffle vectors even when the newly generated vector and the original vector from which we extract the values are of different types. llvm-svn: 150340
* Put instruction names into an indexed string table on the side, removing a ↵Benjamin Kramer2012-02-101-1/+1
| | | | | | | | | pointer from MCInstrDesc. Make them accessible through MCInstrInfo. They are only used for debugging purposes so this doesn't have an impact on performance. X86MCTargetDesc.o goes from 630K to 461K on x86_64. llvm-svn: 150245
* [unwind removal] Remove all of the code for the dead 'unwind' instruction. ThereBill Wendling2012-02-063-7/+0
| | | | | | | were no 'unwind' instructions being generated before this, so this is in effect a no-op. llvm-svn: 149906
* Add additional documentation to the extract-and-trunc dagcombine optimization.Nadav Rotem2012-02-051-3/+8
| | | | llvm-svn: 149823
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-055-22/+20
| | | | llvm-svn: 149816
* reapply the patches reverted in r149470 that reenable ConstantDataArray,Chris Lattner2012-02-051-17/+15
| | | | | | | | | but with a critical fix to the SelectionDAG code that optimizes copies from strings into immediate stores: the previous code was stopping reading string data at the first nul. Address this by adding a new argument to llvm::getConstantStringInfo, preserving the behavior before the patch. llvm-svn: 149800
* [fast-isel] HandlePHINodesInSuccessorBlocks() can promite i8 and i16 types too.Chad Rosier2012-02-041-2/+2
| | | | llvm-svn: 149730
* Handle all live physreg defs in the same place.Jakob Stoklund Olesen2012-02-031-43/+46
| | | | | | | | | | | SelectionDAG has 4 different ways of passing physreg defs to users. Collect all of the uses at the same time, and pass all of them to MI->setPhysRegsDeadExcept() to mark the remaining defs dead. The setPhysRegsDeadExcept() function will soon add the required implicit-defs to instructions with register mask operands. llvm-svn: 149708
* The type-legalizer often scalarizes code. One of the common patterns is ↵Nadav Rotem2012-02-031-0/+34
| | | | | | | | | extract-and-truncate. In this patch we optimize this pattern and convert the sequence into extract op of a narrow type. This allows the BUILD_VECTOR dag optimizations to construct efficient shuffle operations in many cases. llvm-svn: 149692
* fix cmakeAndrew Trick2012-02-011-1/+1
| | | | llvm-svn: 149553
* VLIW specific scheduler framework that utilizes deterministic finite ↵Andrew Trick2012-02-014-1/+938
| | | | | | | | | | automaton (DFA). This new scheduler plugs into the existing selection DAG scheduling framework. It is a top-down critical path scheduler that tracks register pressure and uses a DFA for pipeline modeling. Patch by Sergei Larin! llvm-svn: 149547
* SwitchInst refactoring.Stepan Dyatkovskiy2012-02-012-9/+9
| | | | | | | | | | | | | | | | | The purpose of refactoring is to hide operand roles from SwitchInst user (programmer). If you want to play with operands directly, probably you will need lower level methods than SwitchInst ones (TerminatorInst or may be User). After this patch we can reorganize SwitchInst operands and successors as we want. What was done: 1. Changed semantics of index inside the getCaseValue method: getCaseValue(0) means "get first case", not a condition. Use getCondition() if you want to resolve the condition. I propose don't mix SwitchInst case indexing with low level indexing (TI successors indexing, User's operands indexing), since it may be dangerous. 2. By the same reason findCaseValue(ConstantInt*) returns actual number of case value. 0 means first case, not default. If there is no case with given value, ErrorIndex will returned. 3. Added getCaseSuccessor method. I propose to avoid usage of TerminatorInst::getSuccessor if you want to resolve case successor BB. Use getCaseSuccessor instead, since internal SwitchInst organization of operands/successors is hidden and may be changed in any moment. 4. Added resolveSuccessorIndex and resolveCaseIndex. The main purpose of these methods is to see how case successors are really mapped in TerminatorInst. 4.1 "resolveSuccessorIndex" was created if you need to level down from SwitchInst to TerminatorInst. It returns TerminatorInst's successor index for given case successor. 4.2 "resolveCaseIndex" converts low level successors index to case index that curresponds to the given successor. Note: There are also related compatability fix patches for dragonegg, klee, llvm-gcc-4.0, llvm-gcc-4.2, safecode, clang. llvm-svn: 149481
* Revert Chris' commits up to r149348 that started causing VMCoreTests unit ↵Argyrios Kyrtzidis2012-02-011-10/+7
| | | | | | | | | | | | | | | | | | | test to fail. These are: r149348 r149351 r149352 r149354 r149356 r149357 r149361 r149362 r149364 r149365 llvm-svn: 149470
* remove the last vestiges of llvm::GetConstantStringInfo, in CodeGen.Chris Lattner2012-01-311-7/+4
| | | | llvm-svn: 149356
* rework this logic to not depend on the last argument to GetConstantStringInfo,Chris Lattner2012-01-311-4/+10
| | | | | | which is going away. llvm-svn: 149348
* Remove the now-dead llvm.eh.exception and llvm.eh.selector intrinsics.Bill Wendling2012-01-312-91/+0
| | | | llvm-svn: 149331
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