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* [SDag switch lowering] Simplify code a bit. No functional change intended.Benjamin Kramer2015-06-041-10/+9
| | | | llvm-svn: 239056
* Pass address space to isLegalAddressingMode in DAGCombinerMatt Arsenault2015-06-041-1/+5
| | | | | | | No test because I don't know of a target that makes use of address spaces and indexed load / store. llvm-svn: 239051
* Switch lowering: fix assert in buildBitTests (PR23738)Hans Wennborg2015-06-041-1/+2
| | | | | | | | When checking (High - Low + 1).sle(BitWidth), BitWidth would be truncated to the size of the left-hand side. In the case of this PR, the left-hand side was i4, so BitWidth=64 got truncated to 0 and the assert failed. llvm-svn: 239048
* Don't create a MIN/MAX node if the underlying compare has more than one use.James Molloy2015-06-041-1/+5
| | | | | | | | | If the compare in a select pattern has another use then it can't be removed, so we'd just be creating repeated code if we created a min/max node. Spotted by Matt Arsenault! llvm-svn: 239037
* [SelectionDAG] Fix PR23603.Sanjoy Das2015-06-021-1/+11
| | | | | | | | | | | | | | | | | | | | | Summary: LLVM's MI level notion of invariant_load is different from LLVM's IR level notion of invariant_load with respect to dereferenceability. The IR notion of invariant_load only guarantees that all *non-faulting* invariant loads result in the same value. The MI notion of invariant load guarantees that the load can be legally moved to any location within its containing function. The MI notion of invariant_load is stronger than the IR notion of invariant_load -- an MI invariant_load is an IR invariant_load + a guarantee that the location being loaded from is dereferenceable throughout the function's lifetime. Reviewers: hfinkel, reames Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10075 llvm-svn: 238881
* [sdag] Add the helper I most want to the DAG -- building a bitcastChandler Carruth2015-05-301-0/+7
| | | | | | | | around a value using its existing SDLoc. Start using this in just one function to save omg lines of code. llvm-svn: 238638
* MC: Clean up MCExpr naming. NFC.Jim Grosbach2015-05-301-1/+1
| | | | llvm-svn: 238634
* SelectionDAG: fix logic for promoting shift typesFiona Glaser2015-05-291-15/+21
| | | | | | | | | | | r238503 fixed the problem of too-small shift types by promoting them during legalization, but the correct solution is to promote only the operands that actually demand promotion. This fixes a crash on an out-of-tree target caused by trying to promote an operand that can't be promoted. llvm-svn: 238632
* Replace push_back(Constructor(foo)) with emplace_back(foo) for non-trivial typesBenjamin Kramer2015-05-292-5/+5
| | | | | | | | | | | | | | | | | | | | If the type isn't trivially moveable emplace can skip a potentially expensive move. It also saves a couple of characters. Call sites were found with the ASTMatcher + some semi-automated cleanup. memberCallExpr( argumentCountIs(1), callee(methodDecl(hasName("push_back"))), on(hasType(recordDecl(has(namedDecl(hasName("emplace_back")))))), hasArgument(0, bindTemporaryExpr( hasType(recordDecl(hasNonTrivialDestructor())), has(constructExpr()))), unless(isInTemplateInstantiation())) No functional change intended. llvm-svn: 238602
* [WinEH] Start inserting state number stores for C++ EHReid Kleckner2015-05-281-371/+3
| | | | | | | | | | | | This moves all the state numbering code for C++ EH to WinEHPrepare so that we can call it from the X86 state numbering IR pass that runs before isel. Now we just call the same state numbering machinery and insert a bunch of stores. It also populates MachineModuleInfo with information about the current function. llvm-svn: 238514
* [SelectionDAG] Scalar shift amounts may require legalizationDavid Majnemer2015-05-281-3/+6
| | | | | | | | | The shift amount may be too small to cope with promoted left hand side, make sure to promote it as well. This fixes PR23664. llvm-svn: 238503
* SelectionDAG: Don't do libcall on div/rem if divrem is customJan Vesely2015-05-271-4/+28
| | | | | | | | | | | | v2: TargetLoweringBase:: -> TargetLowering:: Use Ops array v3: Explicitly use value 0 for ?DIV Remove redundant newline Differential revision: http://reviews.llvm.org/D7803 reviewer: ab llvm-svn: 238336
* Added promotion to EXTRACT_SUBVECTOR operand.Elena Demikhovsky2015-05-252-0/+12
| | | | | | | I encountered with this case in one of KNL tests for i1 vectors. v16i1 = EXTRACT_SUBVECTOR v32i1, x llvm-svn: 238130
* Add target hook to allow merging stores of nonzero constantsMatt Arsenault2015-05-241-3/+10
| | | | | | | | | | On GPU targets, materializing constants is cheap and stores are expensive, so only doing this for zero vectors was silly. Most of the new testcases aren't optimally merged, and are for later improvements. llvm-svn: 238108
* SDAG: Give SDDbgValues their own allocator (and reset it)Duncan P. N. Exon Smith2015-05-221-3/+4
| | | | | | | | | | | | Previously `SDDbgValue`s used the general allocator that lives for all of `SelectionDAG`. Instead, give them their own allocator, and reset it whenever `SDDbgInfo::clear()` is called, plugging a spiritual leak. This drops `SelectionDAGBuilder::visitIntrinsicCall()` off of my heap profile (was at around 2% of `llc` for codegen of `-flto -g`). Thanks to Pete Cooper for spotting the problem and suggesting the fix. llvm-svn: 237998
* SDAG: Cleanup initialization of SDDbgValue, NFCDuncan P. N. Exon Smith2015-05-221-9/+7
| | | | | | | | Cleanup how `SDDbgValue` is initialized, and rearrange the fields to save two pointers in the struct layout. No real functionality change though (and I doubt the memory savings would show up in a profile). llvm-svn: 237997
* [X86][SSE] Improve support for 128-bit vector sign extensionSimon Pilgrim2015-05-212-7/+47
| | | | | | | | | | This patch improves support for sign extension of the lower lanes of vectors of integers by making use of the SSE41 pmovsx* sign extension instructions where possible, and optimizing the sign extension by shifts on pre-SSE41 targets (avoiding the use of i64 arithmetic shifts which require scalarization). It converts SIGN_EXTEND nodes to SIGN_EXTEND_VECTOR_INREG where necessary, that more closely matches the pmovsx* instruction than the default approach of using SIGN_EXTEND_INREG which splits the operation (into an ANY_EXTEND lowered to a shuffle followed by shifts) making instruction matching difficult during lowering. Necessary support for SIGN_EXTEND_VECTOR_INREG has been added to the DAGCombiner. Differential Revision: http://reviews.llvm.org/D9848 llvm-svn: 237885
* Fix build warningAndrew Kaylor2015-05-201-1/+1
| | | | llvm-svn: 237855
* [WinEH] C++ EH state numbering fixesAndrew Kaylor2015-05-201-52/+179
| | | | | | Differential Revision: http://reviews.llvm.org/D9787 llvm-svn: 237854
* DAGCombiner: Continue combining if FoldConstantArithmetic() fails.Matthias Braun2015-05-202-74/+106
| | | | | | | | | | | | DAG.FoldConstantArithmetic() can fail even though both operands are Constants if OpaqueConstants are involved. Continue trying other combine possibilities in tis case. Differential Revision: http://reviews.llvm.org/D6946 Somewhat related to PR21801 / rdar://19211454 llvm-svn: 237822
* Fix icmp loweringPawel Bylica2015-05-201-1/+2
| | | | | | | | | | | | | | | | | | | Summary: During icmp lowering it can happen that a constant value can be larger than expected (see the code around the change). APInt::getMinSignedBits() must be checked again as the shift before can change the constant sign to positive. I'm not sure it is the best fix possible though. Test Plan: Regression test included. Reviewers: resistor, chandlerc, spatel, hfinkel Reviewed By: hfinkel Subscribers: hfinkel, llvm-commits Differential Revision: http://reviews.llvm.org/D9147 llvm-svn: 237812
* Change Function::getIntrinsicID() to return an Intrinsic::ID. NFC.Pete Cooper2015-05-201-1/+1
| | | | | | | | Now that Intrinsic::ID is a typed enum, we can forward declare it and so return it from this method. This updates all users which were either using an unsigned to store it, or had a now unnecessary cast. llvm-svn: 237810
* [StatepointLowering] Support of the gc.relocates for invoke statepoints.Igor Laevsky2015-05-203-53/+78
| | | | | | | | | | This change implements support for lowering of the gc.relocates tied to the invoke statepoint. This is acomplished by storing frame indices of the lowered values in "StatepointRelocatedValues" map inside FunctionLoweringInfo instead of storing them in per-basic block structure StatepointLowering. After this change StatepointLowering is used only during "LowerStatepoint" call and it is not necessary to store it as a field in SelectionDAGBuilder anymore. Differential Revision: http://reviews.llvm.org/D7798 llvm-svn: 237786
* Remove a stale commentPhilip Reames2015-05-191-3/+0
| | | | | | The todo was implemented a while ago; I just forgot to remove the comment. llvm-svn: 237736
* use 'auto *' for pointers; clearer usage, no deep copyingSanjay Patel2015-05-191-2/+2
| | | | llvm-svn: 237719
* tidy upSanjay Patel2015-05-191-5/+5
| | | | | | | | 1. remove duplicate local variable 2. add local variable with name to match comment 3. remove useless comment llvm-svn: 237715
* use range-based for-loopSanjay Patel2015-05-191-7/+4
| | | | llvm-svn: 237711
* use range-based for loopSanjay Patel2015-05-191-5/+5
| | | | llvm-svn: 237705
* SelectionDAG: Cleanup and simplify FoldConstantArithmeticMatthias Braun2015-05-191-100/+91
| | | | | | | | | | | This cleans up the FoldConstantArithmetic code by factoring out the case of two ConstantSDNodes into an own function. This avoids unnecessary complexity for many callers who already have ConstantSDNode arguments. This also avoids an intermeidate SmallVector datastructure and a loop over that datastructure. llvm-svn: 237651
* DAGCombiner: Factor common pattern into isOneConstant() function. NFCMatthias Braun2015-05-191-35/+32
| | | | llvm-svn: 237645
* DAGCombiner: Factor common pattern into isAllOnesConstant() function. NFCMatthias Braun2015-05-191-46/+43
| | | | llvm-svn: 237644
* DAGCombiner: Use isNullConstant() where possibleMatthias Braun2015-05-191-19/+13
| | | | llvm-svn: 237643
* Revert accidental change in r237633Matthias Braun2015-05-181-1/+1
| | | | llvm-svn: 237635
* DAGCombiner: Factor common pattern into isNullConstant() function. NFCMatthias Braun2015-05-181-71/+59
| | | | llvm-svn: 237633
* MC: Clean up method names in MCContext.Jim Grosbach2015-05-181-2/+2
| | | | | | | The naming was a mish-mash of old and new style. Update to be consistent with the new. NFC. llvm-svn: 237594
* Preserve the order of READ_REGISTER and WRITE_REGISTERHal Finkel2015-05-182-5/+9
| | | | | | | | | | | | | At the present time, we don't have a way to represent general dependency relationships, so everything is represented using memory dependency. In order to preserve the data dependency of a READ_REGISTER on WRITE_REGISTER, we need to model WRITE_REGISTER as writing (which we had been doing) and model READ_REGISTER as reading (which we had not been doing). Fix this, and also the way that the chain operands were generated at the SDAG level. Patch by Nicholas Paul Johnson, thanks! Test case by me. llvm-svn: 237584
* Revert r237579, as it broke windows buildbotsOliver Stannard2015-05-181-1/+2
| | | | llvm-svn: 237583
* [LLVM - ARM/AArch64] Add ACLE special register intrinsicsOliver Stannard2015-05-181-2/+1
| | | | | | | | | | | | | | | | | | | This patch implements LLVM support for the ACLE special register intrinsics in section 10.1, __arm_{w,r}sr{,p,64}. This patch is intended to lower the read/write_register instrinsics, used to implement the special register intrinsics in the clang patch for special register intrinsics (see http://reviews.llvm.org/D9697), to ARM specific instructions MRC,MCR,MSR etc. to allow reading an writing of coprocessor registers in AArch32 and AArch64. This is done by inspecting the register string passed to the intrinsic and then lowering to the appropriate instruction. Patch by Luke Cheeseman. Differential Revision: http://reviews.llvm.org/D9699 llvm-svn: 237579
* [DAGCombine] Be more pedantic about use iteration in ↵Hal Finkel2015-05-181-11/+12
| | | | | | | | | | | | | | | | | | | | | | | CombineToPreIndexedLoadStore In CombineToPreIndexedLoadStore, when the offset is a constant, we have code that looks for other uses of the pointer which are constant offset computations so that they can be rewritten in terms of the updated pointer so that we don't need to keep a copy of the base pointer to compute these constant offsets. Unfortunately, when it iterated over the uses, it did so by SDNodes, and so we could confuse ourselves if the base pointer was produced by a node that had multiple results (because we would not immediately exclude uses of the other node results). This was reported as PR22755. Unfortunately, we don't have a test case (and I've also been unable to produce one thus far), but at least the mistake is clear. The right way to fix this problem is to make use of the information contained in the use iterators to filter out any uses of other results of the node producing the base pointer. This should be mostly NFC, but should also fix PR22755 (for which, unfortunately, we have no in-tree test case). llvm-svn: 237576
* [WinEH] Push unique_ptr through the Action interface.Benjamin Kramer2015-05-161-21/+15
| | | | | | | This was the source of many leaks in the past, this should fix them once and for all. llvm-svn: 237524
* [SDAGBuilder] Make the AArch64 builder happier.James Molloy2015-05-151-4/+4
| | | | | | | | I intended this loop to only unwrap SplitVector actions, but it was more broad than that, such as unwrapping WidenVector actions, which makes operations seem legal when they're not. llvm-svn: 237457
* Add SDNodes for umin, umax, smin and smax.James Molloy2015-05-156-9/+73
| | | | | | | | | | | | | This adds new SDNodes for signed/unsigned min/max. These nodes are built from select/icmp pairs matched at SDAGBuilder stage. This patch adds the nodes, as well as legalization support and sets them to be "expand" for all targets. NFC for now; this will be tested when I switch AArch64 to using these new nodes. llvm-svn: 237423
* Revert r237046. See the testcase on the thread where r237046 was committed.Nick Lewycky2015-05-134-56/+52
| | | | llvm-svn: 237317
* [DebugInfo] Debug locations for constant SD nodesSergey Dmitrouk2015-05-131-41/+76
| | | | | | | | | | | | | | | | | | | | | Several updates for [DebugInfo] Add debug locations to constant SD nodes (r235989). Includes: * re-enabling the change (disabled recently); * missing change for FP constants; * resetting debug location of constant node if it's used more than at one place to prevent emission of wrong locations in case of coalesced constants; * a couple of additional tests. Now all look ups in CSEMap are wrapped by additional method. Comment in D9084 suggests that debug locations aren't useful for "target constants", so there might be one more change related to this API (namely, dropping debug locations for getTarget*Constant methods). Differential Revision: http://reviews.llvm.org/D9604 llvm-svn: 237237
* [Statepoints] Support for "patchable" statepoints.Sanjoy Das2015-05-121-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change adds two new parameters to the statepoint intrinsic, `i64 id` and `i32 num_patch_bytes`. `id` gets propagated to the ID field in the generated StackMap section. If the `num_patch_bytes` is non-zero then the statepoint is lowered to `num_patch_bytes` bytes of nops instead of a call (the spill and reload code remains unchanged). A non-zero `num_patch_bytes` is useful in situations where a language runtime requires complete control over how a call is lowered. This change brings statepoints one step closer to patchpoints. With some additional work (that is not part of this patch) it should be possible to get rid of `TargetOpcode::STATEPOINT` altogether. PlaceSafepoints generates `statepoint` wrappers with `id` set to `0xABCDEF00` (the old default value for the ID reported in the stackmap) and `num_patch_bytes` set to `0`. This can be made more sophisticated later. Reviewers: reames, pgavlin, swaroop.sridhar, AndyAyers Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9546 llvm-svn: 237214
* [Statepoints] Clean up statepoint argument accessors.Pat Gavlin2015-05-121-22/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D9622 llvm-svn: 237191
* [Statepoints] Split the calling convention and statepoint flags operand to ↵Pat Gavlin2015-05-121-22/+15
| | | | | | | | STATEPOINT into two separate operands. Differential Revision: http://reviews.llvm.org/D9623 llvm-svn: 237166
* Reverse ordering of base and derived pointer during safepoint lowering.Igor Laevsky2015-05-121-10/+12
| | | | | | | | According to the documentation in StackMap section for the safepoint we should have: "The first Location in each pair describes the base pointer for the object. The second is the derived pointer actually being relocated." But before this change we emitted them in reverse order - derived pointer first, base pointer second. llvm-svn: 237126
* Migrate existing backends that care about software floating pointEric Christopher2015-05-121-1/+1
| | | | | | | | | | | | | | | | | | | | to use the information in the module rather than TargetOptions. We've had and clang has used the use-soft-float attribute for some time now so have the backends set a subtarget feature based on a particular function now that subtargets are created based on functions and function attributes. For the one middle end soft float check go ahead and create an overloadable TargetLowering::useSoftFloat function that just checks the TargetSubtargetInfo in all cases. Also remove the command line option that hard codes whether or not soft-float is set by using the attribute for all of the target specific test cases - for the generic just go ahead and add the attribute in the one case that showed up. llvm-svn: 237079
* propagate IR-level fast-math-flags to DAG nodes; 2nd try; NFCSanjay Patel2015-05-114-52/+56
| | | | | | | | | | | | | | | | | | | | | | | This is a less ambitious version of: http://reviews.llvm.org/rL236546 because that was reverted in: http://reviews.llvm.org/rL236600 because it caused memory corruption that wasn't related to FMF but was actually due to making nodes with 2 operands derive from a plain SDNode rather than a BinarySDNode. This patch adds the minimum plumbing necessary to use IR-level fast-math-flags (FMF) in the backend without actually using them for anything yet. This is a follow-on to: http://reviews.llvm.org/rL235997 ...which split the existing nsw / nuw / exact flags and FMF into their own struct. llvm-svn: 237046
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