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* Delete a directory that wasn't supposed to be checked in yet.Micah Villmow2012-10-242-2/+2
| | | | llvm-svn: 166591
* Add in support for getIntPtrType to get the pointer type based on the ↵Micah Villmow2012-10-242-6/+8
| | | | | | | | | address space. This checkin also adds in some tests that utilize these paths and updates some of the clients. llvm-svn: 166578
* Teach DAG combine to fold (buildvec (Xint2fp x)) to (Xint2fp (buildvec x))Michael Liao2012-10-241-0/+71
| | | | | | | | - If more than 1 elemennts are defined and target supports the vectorized conversion, use the vectorized one instead to reduce the strength on conversion operation. llvm-svn: 166546
* Keep coding standard. Don't evaluate getNumOperands() every time.Jakub Staszak2012-10-241-1/+1
| | | | llvm-svn: 166531
* Clean up code and put transformation on (build_vec (ext x)) into a helper funcMichael Liao2012-10-231-55/+69
| | | | llvm-svn: 166519
* Make the indirect branch optimization deterministic. No functionality change.Nadav Rotem2012-10-231-8/+8
| | | | | | Patch by Daniel Reynaud. llvm-svn: 166501
* Symbol hygiene: Make sure declarations and definitions match, make helper ↵Benjamin Kramer2012-10-201-0/+2
| | | | | | functions static. llvm-svn: 166376
* 1. Remove noreturn attribute from __builtin_debugtrap().Shuxin Yang2012-10-191-2/+2
| | | | | | | | (The change at Clang side was committed in r166345) 2. Cosmetic change in order to conform to coding standards. llvm-svn: 166350
* This patch is to fix radar://8426430. It is about llvm support of ↵Shuxin Yang2012-10-193-5/+23
| | | | | | | | | | | | | | | | | | | | | | | __builtin_debugtrap() which is supposed to consistently raise SIGTRAP across all systems. In contrast, __builtin_trap() behave differently on different systems. e.g. it raises SIGTRAP on ARM, and SIGILL on X86. The purpose of __builtin_debugtrap() is to consistently provide "trap" functionality, in the mean time preserve the compatibility with on gcc on __builtin_trap(). The X86 backend is already able to handle debugtrap(). This patch is to: 1) make front-end recognize "__builtin_debugtrap()" (emboddied in the one-line change to Clang). 2) In DAG legalization phase, by default, "debugtrap" will be replaced with "trap", which make the __builtin_debugtrap() "available" to all existing ports without the hassle of changing their code. 3) If trap-function is specified (via -trap-func=xyz to llc), both __builtin_debugtrap() and __builtin_trap() will be expanded into the function call of the specified trap function. This behavior may need change in the future. The provided testing-case is to make sure 2) and 3) are working for ARM port, and we already have a testing case for x86. llvm-svn: 166300
* Simplify condition checking as CONCAT assume all inputs of the same type.Michael Liao2012-10-191-3/+3
| | | | llvm-svn: 166260
* In SimplifySelectOps we pulled two loads through a select node despite the ↵Nadav Rotem2012-10-181-0/+4
| | | | | | | | fact that one was dependent on the other. rdar://12513091 llvm-svn: 166196
* Revert part of r166049 back and enable test case in r166125.Michael Liao2012-10-171-0/+42
| | | | | | | | - Folding (trunc (concat ... X )) to (concat ... (trunc X) ...) is valid when '...' are all 'undef's. - r166125 relies on this transformation. llvm-svn: 166155
* Revert r166049Michael Liao2012-10-171-46/+0
| | | | | | - In general, it's unsafe for this transformation. llvm-svn: 166135
* Teach DAG combine to fold (extract_subvec (concat v1, ..) i) to v_iMichael Liao2012-10-171-2/+17
| | | | | | | | - If the extracted vector has the same type of all vectored being concatenated together, it should be simplified directly into v_i, where i is the index of the element being extracted. llvm-svn: 166125
* Add a really faster pre-RA scheduler (-pre-RA-sched=linearize). It doesn't useEvan Cheng2012-10-173-3/+160
| | | | | | | | | | | | | | any scheduling heuristics nor does it build up any scheduling data structure that other heuristics use. It essentially linearize by doing a DFA walk but it does handle glues correctly. IMPORTANT: it probably can't handle all the physical register dependencies so it's not suitable for x86. It also doesn't deal with dbg_value nodes right now so it's definitely is still WIP. rdar://12474515 llvm-svn: 166122
* Teach DAG combine to fold (trunc (fptoXi x)) to (fptoXi x)Michael Liao2012-10-161-0/+46
| | | | llvm-svn: 166049
* Freeze the reserved registers as soon as isel is complete.Jakob Stoklund Olesen2012-10-151-0/+5
| | | | | | | | | | | | | Also provide an MRI::getReservedRegs() function to access the frozen register set, and isReserved() and isAllocatable() methods to test individual registers. The various implementations of TRI::getReservedRegs() are quite complicated, and many passes need to look at the reserved register set. This patch makes it possible for these passes to use the cached copy in MRI, avoiding a lot of malloc traffic and repeated calculations. llvm-svn: 165982
* Resubmit the changes to llvm core to update the functions to support ↵Micah Villmow2012-10-151-1/+4
| | | | | | different pointer sizes on a per address space basis. llvm-svn: 165941
* Fix big-endian codegen bug in DAGTypeLegalizer::ExpandRes_BITCASTUlrich Weigand2012-10-121-0/+4
| | | | | | | | | | | | | | | | | | | | | | On PowerPC, a bitcast of <16 x i8> to i128 may run through a code path in ExpandRes_BITCAST that attempts to do an intermediate bitcast to a <4 x i32> vector, and then construct the Hi and Lo parts of the resulting i128 by pairing up two of those i32 vector elements each. The code already recognizes that on a big-endian system, the first two vector elements form the Hi part, and the final two vector elements form the Lo part (vice-versa from the little-endian situation). However, we also need to take endianness into account when forming each of those separate pairs: on a big-endian system, vector element 0 is the *high* part of the pair making up the Hi part of the result, and vector element 1 is the low part of the pair. The code currently always uses vector element 0 as the low part and vector element 1 as the high part, as is appropriate for little-endian platforms only. This patch fixes this by swapping the vector elements as they are paired up as appropriate. llvm-svn: 165802
* Legalizer optimize a pair of div / mod to a call to divrem libcall if they areEvan Cheng2012-10-121-0/+2
| | | | | | | | | | not legal. However, it should use a div instruction + mul + sub if divide is legal. The rem legalization code was missing a check and incorrectly uses a divrem libcall even when div is legal. rdar://12481395 llvm-svn: 165778
* Revert 165732 for further review.Micah Villmow2012-10-111-4/+1
| | | | llvm-svn: 165747
* Add in the first iteration of support for llvm/clang/lldb to allow variable ↵Micah Villmow2012-10-111-1/+4
| | | | | | per address space pointer sizes to be optimized correctly. llvm-svn: 165726
* Follow the same routine to add target float expansion hookMichael Liao2012-10-111-26/+24
| | | | llvm-svn: 165707
* Add in support for expansion of all of the comparison operations to the ↵Micah Villmow2012-10-101-17/+62
| | | | | | | | | | absolute minimum required set. This allows a backend to expand any arbitrary set of comparisons as long as a minimum set is supported. The minimum set of required instructions is ISD::AND, ISD::OR, ISD::SETO(or ISD::SETOEQ) and ISD::SETUO(or ISD::SETUNE). Everything is expanded into one of two patterns: Pattern 1: (LHS CC1 RHS) Opc (LHS CC2 RHS) Pattern 2: (LHS CC1 LHS) Opc (RHS CC2 RHS) llvm-svn: 165655
* Add alternative support for FP_ROUND from v2f32 to v2f64Michael Liao2012-10-102-4/+8
| | | | | | | | | | | - Due to the current matching vector elements constraints in ISD::FP_EXTEND, rounding from v2f32 to v2f64 is scalarized. Add a customized v2f32 widening to convert it into a target-specific X86ISD::VFPEXT to work around this constraints. This patch also reverts a previous attempt to fix this issue by recovering the scalarized ISD::FP_EXTEND pattern and thus significantly reduces the overhead of supporting non-power-2 vector FP extend. llvm-svn: 165625
* Issue description:Stepan Dyatkovskiy2012-10-101-2/+3
| | | | | | | | | | | | | | | | | | | | SchedulerDAGInstrs::buildSchedGraph ignores dependencies between FixedStack objects and byval parameters. So loading byval parameters from stack may be inserted *before* it will be stored, since these operations are treated as independent. Fix: Currently ARMTargetLowering::LowerFormalArguments saves byval registers with FixedStack MachinePointerInfo. To fix the problem we need to store byval registers with MachinePointerInfo referenced to first the "byval" parameter. Also commit adds two new fields to the InputArg structure: Function's argument index and InputArg's part offset in bytes relative to the start position of Function's argument. E.g.: If function's argument is 128 bit width and it was splitted onto 32 bit regs, then we got 4 InputArg structs with same arg index, but different offset values. llvm-svn: 165616
* Use the attribute enums to query if a parameter has an attribute.Bill Wendling2012-10-091-6/+6
| | | | llvm-svn: 165550
* Add in the first step of the multiple pointer support. This adds in support ↵Micah Villmow2012-10-091-6/+7
| | | | | | | | to the data layout for specifying a per address space pointer size. The next step is to update the optimizers to allow them to optimize the different address spaces with this information. llvm-svn: 165505
* Create enums for the different attributes.Bill Wendling2012-10-093-20/+24
| | | | | | | We use the enums to query whether an Attributes object has that attribute. The opaque layer is responsible for knowing where that specific attribute is stored. llvm-svn: 165488
* Refactor the AddrMode class out of TLI to its own header file.Nadav Rotem2012-10-081-1/+1
| | | | | | | | This class is used by LSR and a number of places in the codegen. This is the first step in de-coupling LSR from TLI, and creating a new interface in between them. llvm-svn: 165455
* misched: remove forceUnitLatencies. Defaults are handled by the default ↵Andrew Trick2012-10-081-0/+6
| | | | | | SchedModel llvm-svn: 165417
* Move TargetData to DataLayout.Micah Villmow2012-10-0816-65/+65
| | | | llvm-svn: 165402
* Remove unused but set variable flagged by GCC.Benjamin Kramer2012-10-051-4/+0
| | | | llvm-svn: 165331
* Simplify code, don't or a bool with an uint64_t.Benjamin Kramer2012-10-051-2/+2
| | | | | | No functionality change. llvm-svn: 165321
* When merging connsecutive stores, use vectors to store the constant zero.Nadav Rotem2012-10-041-34/+57
| | | | llvm-svn: 165267
* Update to use the predicate methods to query if an attribute exists.Bill Wendling2012-10-031-17/+17
| | | | llvm-svn: 165163
* Fix a cycle in the DAG. In this code we replace multiple loads with a single ↵Nadav Rotem2012-10-031-7/+19
| | | | | | | | | | | load and multiple stores with a single load. We create the wide loads and stores (and their chains) before we remove the scalar loads and stores and fix the DAG chain. We attempted to merge loads with a different chain. When that happened, the assumption that it is safe to RAUW broke and a cycle was introduced. llvm-svn: 165148
* A DAGCombine optimization for mergeing consecutive stores to memory. The ↵Nadav Rotem2012-10-031-0/+395
| | | | | | | | | | | | | | | | | | | | | optimization is not profitable in many cases because modern processors perform multiple stores in parallel and merging stores prior to merging requires extra work. We handle two main cases: 1. Store of multiple consecutive constants: q->a = 3; q->4 = 5; In this case we store a single legal wide integer. 2. Store of multiple consecutive loads: int a = p->a; int b = p->b; q->a = a; q->b = b; In this case we load/store either ilegal vector registers or legal wide integer registers. llvm-svn: 165125
* Revert 165051-165049 while looking into the foreach.m failure inEric Christopher2012-10-031-16/+11
| | | | | | more detail. llvm-svn: 165099
* Remove the SavePoint infrastructure from fast isel, replaceEric Christopher2012-10-021-11/+16
| | | | | | | with just an insert point from the MachineBasicBlock and let the location be updated as we access it. llvm-svn: 165049
* Fix PR13991: legalizing an overflowing multiplication operation is harder thanDuncan Sands2012-10-021-7/+15
| | | | | | | the add/sub case since in the case of multiplication you also have to check that the operation in the larger type did not overflow. llvm-svn: 165017
* Use dyn_cast instead of isa and cast.Jakub Staszak2012-09-301-10/+8
| | | | | | No functionality change. llvm-svn: 164924
* Revert r164910 because it causes failures to several phase2 builds.Nadav Rotem2012-09-301-254/+0
| | | | llvm-svn: 164911
* A DAGCombine optimization for merging consecutive stores. This optimization ↵Nadav Rotem2012-09-301-0/+254
| | | | | | | | | | | | | | | | | | | is not profitable in many cases because moden processos can store multiple values in parallel, and preparing the consecutive store requires some work. We only handle these cases: 1. Consecutive stores where the values and consecutive loads. For example: int a = p->a; int b = p->b; q->a = a; q->b = b; 2. Consecutive stores where the values are constants. Foe example: q->a = 4; q->b = 5; llvm-svn: 164910
* Speculatively revert commit 164885 (nadav) in the hope of ressurecting a pile ofDuncan Sands2012-09-291-252/+0
| | | | | | | | | | | | | | | | | | | | buildbots. Original commit message: A DAGCombine optimization for merging consecutive stores. This optimization is not profitable in many cases because moden processos can store multiple values in parallel, and preparing the consecutive store requires some work. We only handle these cases: 1. Consecutive stores where the values and consecutive loads. For example: int a = p->a; int b = p->b; q->a = a; q->b = b; 2. Consecutive stores where the values are constants. Foe example: q->a = 4; q->b = 5; llvm-svn: 164890
* Tidy up to match coding standards. Remove 'else' after 'return' and moving ↵Craig Topper2012-09-291-27/+24
| | | | | | operators to end of preceding line. No functional change intended. llvm-svn: 164887
* Replace a couple if/elses around similar calls with conditional operators on ↵Craig Topper2012-09-291-17/+6
| | | | | | the varying arguments. No functional change. llvm-svn: 164886
* A DAGCombine optimization for merging consecutive stores. This optimization ↵Nadav Rotem2012-09-291-0/+252
| | | | | | | | | | | | | | | | | | | is not profitable in many cases because moden processos can store multiple values in parallel, and preparing the consecutive store requires some work. We only handle these cases: 1. Consecutive stores where the values and consecutive loads. For example: int a = p->a; int b = p->b; q->a = a; q->b = b; 2. Consecutive stores where the values are constants. Foe example: q->a = 4; q->b = 5; llvm-svn: 164885
* Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. ↵Sylvestre Ledru2012-09-274-35/+35
| | | | | | See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767 llvm-svn: 164768
* Fix a typo 'iff' => 'if'Sylvestre Ledru2012-09-274-35/+35
| | | | llvm-svn: 164767
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