summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/SelectionDAG
Commit message (Collapse)AuthorAgeFilesLines
* Fix a crash in the dag combiner caused by ↵Nate Begeman2010-07-271-2/+10
| | | | | | | | ConstantFoldBIT_CONVERTofBUILD_VECTOR calling itself recursively and returning a SCALAR_TO_VECTOR node, but assuming the input was always a BUILD_VECTOR. llvm-svn: 109519
* It's better to have the arrays, which would trigger the creation of stackBill Wendling2010-07-271-1/+9
| | | | | | | | | protectors, to be near the stack protectors on the stack. Accomplish this by tagging the stack object with a predicate that indicates that it would trigger this. In the prolog-epilog inserter, assign these objects to the stack after the stack protector but before the other objects. llvm-svn: 109481
* The "excess register pressure" returned by HighRegPressure() is not accurate ↵Evan Cheng2010-07-261-41/+20
| | | | | | enough to factor into scheduling priority. Eliminate it and add early exits to speed up scheduling. llvm-svn: 109449
* Handle Values with no value in getCopyFromRegs.Dan Gohman2010-07-261-0/+4
| | | | llvm-svn: 109415
* Pacify gcc-4.5 which wrongly thinks that RExcess (passed as the Excess ↵Duncan Sands2010-07-261-1/+2
| | | | | | | | parameter) may be used uninitialized in the callers of HighRegPressure. llvm-svn: 109393
* Add comments.Evan Cheng2010-07-251-4/+16
| | | | llvm-svn: 109383
* Fix crashes when scheduling a CopyToReg node -- getMachineOpcode asserts onBob Wilson2010-07-251-2/+2
| | | | | | those. Radar 8231572. llvm-svn: 109367
* Add an ILP scheduler. This is a register pressure aware scheduler that'sEvan Cheng2010-07-242-12/+76
| | | | | | | | | | | | appropriate for targets without detailed instruction iterineries. The scheduler schedules for increased instruction level parallelism in low register pressure situation; it schedules to reduce register pressure when the register pressure becomes high. On x86_64, this is a win for all tests in CFP2000. It also sped up 256.bzip2 by 16%. llvm-svn: 109300
* - Allow target to specify when is register pressure "too high". In most cases,Evan Cheng2010-07-231-56/+124
| | | | | | | | | | | | | it's too late to start backing off aggressive latency scheduling when most of the registers are in use so the threshold should be a bit tighter. - Correctly handle live out's and extract_subreg etc. - Enable register pressure aware scheduling by default for hybrid scheduler. For ARM, this is almost always a win on # of instructions. It's runtime neutral for most of the tests. But for some kernels with high register pressure it can be a huge win. e.g. 464.h264ref reduced number of spills by 54 and sped up by 20%. llvm-svn: 109279
* Use the proper type for shift counts. This fixes a bootstrap error.Dan Gohman2010-07-231-1/+4
| | | | llvm-svn: 109265
* DAGCombine (shl (anyext x, c)) to (anyext (shl x, c)) if the high bitsDan Gohman2010-07-231-1/+21
| | | | | | are not demanded. This often allows the anyext to be folded away. llvm-svn: 109242
* Make SDNode::dump() print a newline at the end.Dan Gohman2010-07-231-0/+1
| | | | llvm-svn: 109234
* 80-col.Eric Christopher2010-07-231-8/+12
| | | | llvm-svn: 109205
* keep in 80 colsGabor Greif2010-07-221-2/+4
| | | | llvm-svn: 109122
* mass elimination of reliance on automatic iterator dereferencingGabor Greif2010-07-222-2/+2
| | | | llvm-svn: 109103
* Re-apply r109079 with fix.Evan Cheng2010-07-221-28/+26
| | | | llvm-svn: 109083
* Revert r109079, which broke a lot of CodeGen tests.Owen Anderson2010-07-221-25/+27
| | | | llvm-svn: 109082
* Initialize RegLimit only when register pressure is being tracked.Evan Cheng2010-07-221-27/+25
| | | | llvm-svn: 109079
* More register pressure aware scheduling work.Evan Cheng2010-07-211-81/+84
| | | | llvm-svn: 109064
* Teach bottom up pre-ra scheduler to track register pressure. Work in progress.Evan Cheng2010-07-212-22/+242
| | | | llvm-svn: 108991
* After a custom inserter, in a block which has constant instructions,Dan Gohman2010-07-191-0/+1
| | | | | | | update the current basic block in addition to the current insert position, so that they remain consistent. This fixes rdar://8204072. llvm-svn: 108765
* ARM has to provide its own TargetLowering::findRepresentativeClass because ↵Evan Cheng2010-07-191-6/+7
| | | | | | its scalar floating point registers alias its vector registers. llvm-svn: 108761
* Teach computeRegisterProperties() to compute "representative" register class ↵Evan Cheng2010-07-191-0/+52
| | | | | | | | for legal value types. A "representative" register class is the largest legal super-reg register class for a value type. e.g. On i386, GR32 is the rep register class for i8 / i16 / i32; on x86_64 it would be GR64. This property will be used by the register pressure tracking instruction scheduler. llvm-svn: 108735
* Remove r108639 now that it is handled by InstCombine instead.Owen Anderson2010-07-191-13/+0
| | | | llvm-svn: 108688
* Add a DAGCombine xform to fold away redundant float->double->float ↵Owen Anderson2010-07-181-0/+13
| | | | | | | | | | conversions around sqrt instructions. I am assured by people more knowledgeable than me that there are no rounding issues in eliminating this. This fixed <rdar://problem/8197504>. llvm-svn: 108639
* Propagate alloca alignment information via variable size object frameEric Christopher2010-07-171-1/+1
| | | | | | | | information. No functional change yet. llvm-svn: 108583
* Revert r108369, sorting llvm.dbg.declare information by source position,Dan Gohman2010-07-163-26/+34
| | | | | | | | | | | | | since it doesn't work for front-ends which don't emit column information (which includes llvm-gcc in its present configuration), and doesn't work for clang for K&R style variables where the variables are declared in a different order from the parameter list. Instead, make a separate pass through the instructions to collect the llvm.dbg.declare instructions in order. This ensures that the debug information for variables is emitted in this order. llvm-svn: 108538
* Use the source-order scheduler instead of the "fast" scheduler at -O0,Dan Gohman2010-07-161-1/+1
| | | | | | | because it's more likely to keep debug line information in its original order. llvm-svn: 108496
* The SelectionDAGBuilder's handling of debug info, on rareDale Johannesen2010-07-162-12/+60
| | | | | | | | | | occasions, caused code to be generated in a different order. All cases I've seen involved float softening in the type legalizer, and this could be perhaps be fixed there, but it's better not to generate things differently in the first place. 7797940 (6/29/2010..7/15/2010). llvm-svn: 108484
* Revert. This isn't the correct way to go.Bill Wendling2010-07-152-15/+1
| | | | llvm-svn: 108478
* Handle code gen for the unreachable instruction if it's the only instruction inBill Wendling2010-07-152-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the function. We'll just turn it into a "trap" instruction instead. The problem with not handling this is that it might generate a prologue without the equivalent epilogue to go with it: $ cat t.ll define void @foo() { entry: unreachable } $ llc -o - t.ll -relocation-model=pic -disable-fp-elim -unwind-tables .section __TEXT,__text,regular,pure_instructions .globl _foo .align 4, 0x90 _foo: ## @foo Leh_func_begin0: ## BB#0: ## %entry pushq %rbp Ltmp0: movq %rsp, %rbp Ltmp1: Leh_func_end0: ... The unwind tables then have bad data in them causing all sorts of problems. Fixes <rdar://problem/8096481>. llvm-svn: 108473
* Split -enable-finite-only-fp-math to two options:Evan Cheng2010-07-151-1/+1
| | | | | | -enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN. llvm-svn: 108465
* Fix crash reported in PR7653.Devang Patel2010-07-151-1/+1
| | | | llvm-svn: 108441
* 80-col.Eric Christopher2010-07-141-2/+3
| | | | llvm-svn: 108381
* Properly restore DebugLoc after leaving the local constant area.Dan Gohman2010-07-141-1/+2
| | | | llvm-svn: 108364
* Delete fast-isel's trivial load optimization; it breaks debugging becauseDan Gohman2010-07-141-31/+0
| | | | | | it can look past points where a debugger might modify user variables. llvm-svn: 108336
* Don't propagate debug locations to instructions for materializingDan Gohman2010-07-141-5/+8
| | | | | | | constants, since they may not be emited near the other instructions which get the same line, and this confuses debug info. llvm-svn: 108302
* In inline asm treat indirect 'X' constraint as 'm'.Dale Johannesen2010-07-131-3/+5
| | | | | | | This may not be right in all cases, but it's better than asserting which it was doing before. PR 7528. llvm-svn: 108268
* Fix a typo and fit in 80 columns. Found by Bob Wilson.Rafael Espindola2010-07-121-1/+2
| | | | llvm-svn: 108164
* Convert some tab stops into spaces.Duncan Sands2010-07-123-30/+30
| | | | llvm-svn: 108130
* Use COPY for fast-isel bitconvert, but don't create cross-class copies.Jakob Stoklund Olesen2010-07-111-7/+6
| | | | | | This doesn't change the behavior of SelectBitcast for X86. llvm-svn: 108073
* Fix va_arg for doubles. With this patch VAARG nodes always contain theRafael Espindola2010-07-116-9/+12
| | | | | | | | | | | | | | | correct alignment information, which simplifies ExpandRes_VAARG a bit. The patch introduces a new alignment information to TargetLoweringInfo. This is needed since the two natural candidates cannot be used: * The 's' in target data: If this is set to the minimal alignment of any argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for example. * The getTransientStackAlignment method. It is possible for an architecture to have argument less aligned than what we maintain the stack pointer. llvm-svn: 108072
* Use COPY for extracting ImplicitDef'ed values from fast-isel instructions.Jakob Stoklund Olesen2010-07-111-30/+12
| | | | | | | This assumes that the registers can be copied which is probably a safe assumption. llvm-svn: 108070
* Use COPY in FastISel everywhere it is safe and trivial.Jakob Stoklund Olesen2010-07-111-8/+4
| | | | | | | The remaining copyRegToReg calls actually check the return value (shock!), so we cannot trivially replace them with COPY instructions. llvm-svn: 108069
* Fix a bug in the code which re-inserts DBG_VALUE nodes after scheduling;Dan Gohman2010-07-101-1/+3
| | | | | | | | if a block is split (by a custom inserter), the insert point may be in a different block than it was originally. This fixes 32-bit llvm-gcc bootstrap builds, and I haven't been able to reproduce it otherwise. llvm-svn: 108060
* Emit COPY instructions instead of using copyRegToReg in InstrEmitter,Jakob Stoklund Olesen2010-07-101-34/+9
| | | | | | | | | ScheduleDAGEmit, TwoAddressLowering, and PHIElimination. This switches the bulk of register copies to using COPY, but many less used copyRegToReg calls remain. llvm-svn: 108050
* Insert IMPLICIT_DEF instructions at the current insert position, notDan Gohman2010-07-101-1/+1
| | | | | | at the end of the block. llvm-svn: 108045
* Reapply bottom-up fast-isel, with several fixes for x86-32:Dan Gohman2010-07-107-246/+371
| | | | | | | | | - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
* Clarify what mysterious check means.Bill Wendling2010-07-091-0/+3
| | | | llvm-svn: 108005
* --- Reverse-merging r107947 into '.':Bob Wilson2010-07-097-371/+246
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | U utils/TableGen/FastISelEmitter.cpp --- Reverse-merging r107943 into '.': U test/CodeGen/X86/fast-isel.ll U test/CodeGen/X86/fast-isel-loads.ll U include/llvm/Target/TargetLowering.h U include/llvm/Support/PassNameParser.h U include/llvm/CodeGen/FunctionLoweringInfo.h U include/llvm/CodeGen/CallingConvLower.h U include/llvm/CodeGen/FastISel.h U include/llvm/CodeGen/SelectionDAGISel.h U lib/CodeGen/LLVMTargetMachine.cpp U lib/CodeGen/CallingConvLower.cpp U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp U lib/CodeGen/SelectionDAG/FastISel.cpp U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp U lib/CodeGen/SelectionDAG/InstrEmitter.cpp U lib/CodeGen/SelectionDAG/TargetLowering.cpp U lib/Target/XCore/XCoreISelLowering.cpp U lib/Target/XCore/XCoreISelLowering.h U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86ISelLowering.h llvm-svn: 107987
OpenPOWER on IntegriCloud