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* When passing a parameter using the 'byval' mechanism, inline code needs to ↵Duncan Sands2010-11-051-0/+2
| | | | | | | | | | | | | be used to perform the copy, which may be of lots of memory [*]. It would be good if the fall-back code generated something reasonable, i.e. did the copy in a loop, rather than vast numbers of loads and stores. Add a note about this. Currently target specific code seems to always kick in so this is more of a theoretical issue rather than a practical one now that X86 has been fixed. [*] It's amazing how often people pass mega-byte long arrays by copy... llvm-svn: 118275
* Just return undef for invalid masks or elts, and since we're doing that,Eric Christopher2010-11-031-5/+6
| | | | | | just do it earlier too. llvm-svn: 118195
* Simplify uses of MVT and EVT. An MVT can be compared directlyDuncan Sands2010-11-032-7/+5
| | | | | | | with a SimpleValueType, while an EVT supports equality and inequality comparisons with SimpleValueType. llvm-svn: 118169
* Inside the calling convention logic LocVT is always a simpleDuncan Sands2010-11-031-3/+3
| | | | | | | | | | value type, so there is no point in passing it around using an EVT. Use the simpler MVT everywhere. Rather than trying to propagate this information maximally in all the code that using the calling convention stuff, I chose to do a mainly low impact change instead. llvm-svn: 118167
* If we have an undef mask our Elt will be -1 for our access, handleEric Christopher2010-11-031-3/+7
| | | | | | | | this by using an undef as a pointer. Fixes rdar://8625016 llvm-svn: 118164
* Fix DAGCombiner to avoid going into an infinite loop when itDan Gohman2010-11-031-1/+36
| | | | | | | encounters (and:i64 (shl:i64 (load:i64), 1), 0xffffffff). This fixes rdar://8606584. llvm-svn: 118143
* Two sets of changes. Sorry they are intermingled.Evan Cheng2010-11-032-4/+15
| | | | | | | | | | | | | 1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to "optimize for latency". Call instructions don't have the right latency and this is more likely to use introduce spills. 2. Fix if-converter cost function. For ARM, it should use instruction latencies, not # of micro-ops since multi-latency instructions is completely executed even when the predicate is false. Also, some instruction will be "slower" when they are predicated due to the register def becoming implicit input. rdar://8598427 llvm-svn: 118135
* If value map does not have register for an argument then try to find frame ↵Devang Patel2010-11-021-5/+8
| | | | | | index before giving up. llvm-svn: 118022
* Use frameindex, if available, as a last resort to emit debug info for a ↵Devang Patel2010-11-021-2/+13
| | | | | | parameter. llvm-svn: 118020
* Remove DAG combiner patch to fold vector splats. Instcombiner does it now.Bob Wilson2010-10-291-5/+0
| | | | llvm-svn: 117720
* Avoiding overly aggressive latency scheduling. If the two nodes share anEvan Cheng2010-10-292-24/+78
| | | | | | | | | | | | | | | | | | | | | | | | | operand and one of them has a single use that is a live out copy, favor the one that is live out. Otherwise it will be difficult to eliminate the copy if the instruction is a loop induction variable update. e.g. BB: sub r1, r3, #1 str r0, [r2, r3] mov r3, r1 cmp bne BB => BB: str r0, [r2, r3] sub r3, r3, #1 cmp bne BB This fixed the recent 256.bzip2 regression. llvm-svn: 117675
* Inline asm multiple alternative constraints development phase 2 - improved ↵John Thompson2010-10-292-46/+76
| | | | | | basic logic, added initial platform support. llvm-svn: 117667
* Teach the DAG combiner to fold a splat of a splat. Radar 8597790.Bob Wilson2010-10-281-24/+28
| | | | | | Also do some minor refactoring to reduce indentation. llvm-svn: 117558
* Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.Evan Cheng2010-10-281-0/+3
| | | | llvm-svn: 117531
* Revert 117518 and 117519 for now. They changed scheduling and cause MC tests ↵Evan Cheng2010-10-281-3/+0
| | | | | | to fail. Ugh. llvm-svn: 117520
* Fix a major bug in operand latency computation. The use index must be adjustedEvan Cheng2010-10-281-0/+3
| | | | | | by the number of defs first for it to match the instruction itinerary. llvm-svn: 117518
* Use a MemIntrinsicSDNode for ISD::PREFETCH, which touchesDale Johannesen2010-10-262-2/+11
| | | | | | | | memory, so a MachineMemOperand is useful (not propagated into the MachineInstr yet). No functional change except for dump output. llvm-svn: 117413
* Assign source ordering to nodes created for StoreInst.Devang Patel2010-10-261-2/+5
| | | | llvm-svn: 117404
* For statistics that are only used in functions declared in !NDEBUG, wrap theNick Lewycky2010-10-261-0/+3
| | | | | | | declarations in !NDEBUG to avoid -Wunused-variable warnings. Patch by Matt Beaumont-Gay! llvm-svn: 117345
* Simplify.Devang Patel2010-10-251-9/+9
| | | | | | Do not count use of sdisel for single call instruction. llvm-svn: 117316
* Add counters to count basic blocks and machine basic blocks with out of ↵Devang Patel2010-10-251-4/+63
| | | | | | | | order line number info. Add counters to count how many basic blocks are entirely selected by fastisel. llvm-svn: 117310
* Move the remaining attribute macros to systematic names based on the attributeChandler Carruth2010-10-231-12/+12
| | | | | | name and prefixed with 'LLVM_'. llvm-svn: 117203
* X86: Base _fltused on the FunctionType of the called value instead of the ↵Michael J. Spencer2010-10-211-19/+20
| | | | | | | | potentially null "CalledFunction". Thanks Duncan! This is needed for indirect calls. llvm-svn: 117061
* CodeGen-Windows: Only emit _fltused if a VarArg function is called with ↵Michael J. Spencer2010-10-211-5/+5
| | | | | | | | floating point args. This should be the minimum set of functions that could possibly need it. llvm-svn: 116978
* Remove Synthesizable from the Type system; as MMX vectorDale Johannesen2010-10-202-11/+11
| | | | | | | types are no longer Legal on X86, we don't need it. No functional change. 8499854. llvm-svn: 116947
* Make CodeGen TBAA-aware.Dan Gohman2010-10-203-21/+42
| | | | llvm-svn: 116890
* Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do anyJim Grosbach2010-10-193-2/+13
| | | | | | | setup they require. Use this for ARM/Darwin to rematerialize the base pointer from the frame pointer when required. rdar://8564268 llvm-svn: 116879
* Get rid of static constructors for pass registration. Instead, every pass ↵Owen Anderson2010-10-191-2/+4
| | | | | | | | | | | | | | | | | exposes an initializeMyPassFunction(), which must be called in the pass's constructor. This function uses static dependency declarations to recursively initialize the pass's dependencies. Clients that only create passes through the createFooPass() APIs will require no changes. Clients that want to use the CommandLine options for passes will need to manually call the appropriate initialization functions in PassInitialization.h before parsing commandline arguments. I have tested this with all standard configurations of clang and llvm-gcc on Darwin. It is possible that there are problems with the static dependencies that will only be visible with non-standard options. If you encounter any crash in pass registration/creation, please send the testcase to me directly. llvm-svn: 116820
* X86-Windows: Emit an undefined global __fltused symbol when targeting WindowsMichael J. Spencer2010-10-161-0/+20
| | | | | | if any floating point arguments are passed to an external function. llvm-svn: 116665
* Whitespace!Michael J. Spencer2010-10-161-46/+46
| | | | llvm-svn: 116664
* fix the default va_arg expansion (in the realignment case) to not implicitlyChris Lattner2010-10-101-1/+1
| | | | | | truncate the stack pointer to 32-bits on a 64-bit machine. llvm-svn: 116169
* ComputeLinearIndex doesn't need its TLI argument.Dan Gohman2010-10-061-4/+2
| | | | llvm-svn: 115792
* - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. ThisEvan Cheng2010-10-061-19/+1
| | | | | | | | | | | | | allow target to correctly compute latency for cases where static scheduling itineraries isn't sufficient. e.g. variable_ops instructions such as ARM::ldm. This also allows target without scheduling itineraries to compute operand latencies. e.g. X86 can return (approximated) latencies for high latency instructions such as division. - Compute operand latencies for those defined by load multiple instructions, e.g. ldm and those used by store multiple instructions, e.g. stm. llvm-svn: 115755
* Use a more efficient lowering of uint64_t --> float that can take advantage ↵Owen Anderson2010-10-051-6/+28
| | | | | | | | | of hardware signed integer conversion without having to do a double cast (uint64_t --> double --> float). This is based on the algorithm from compiler_rt's __floatundisf for X86-64. llvm-svn: 115634
* This DAG combine BRCOND transformation can look pass truncate of the operand:Evan Cheng2010-10-041-13/+18
| | | | | | | | | | | | | | | | | | | | // %a = ... // %b = and i32 %a, 2 // %c = srl i32 %b, 1 // brcond i32 %c ... // // into // // %a = ... // %b = and i32 %a, 2 // %c = setcc eq %b, 0 // brcond %c ... Make sure it restores local variable N1, which corresponds to the condition operand if it fails to match. This apparently breaks TCE but since that backend isn't in the tree I don't have a test for it. llvm-svn: 115571
* Fix code gen crash reported in PR 8235. We still lose debug info for the ↵Devang Patel2010-10-011-0/+3
| | | | | | unused argument here. This is a known limitation recorded debuginfo-tests/trunk/dbg-declare2.ll function 'f6' test case. llvm-svn: 115323
* typoGabor Greif2010-10-011-1/+1
| | | | llvm-svn: 115310
* fix typoChris Lattner2010-10-011-1/+1
| | | | llvm-svn: 115300
* fix rdar://8494845 + PR8244 - a miscompile exposed by my patch in r101350Chris Lattner2010-10-011-0/+9
| | | | llvm-svn: 115294
* Massive rewrite of MMX: Dale Johannesen2010-09-301-0/+60
| | | | | | | | | | | | | | | | | | | The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. llvm-svn: 115243
* When isel is emitting instructions for an x86 target without CMOV, the CFG isJakob Stoklund Olesen2010-09-303-1/+24
| | | | | | | | | | | | | | | | | edited during emission. If the basic block ends in a switch that gets lowered to a jump table, any phis at the default edge were getting updated wrong. The jump table data structure keeps a pointer to the header blocks that wasn't getting updated after the MBB is split. This bug was exposed on 32-bit Linux when disabling critical edge splitting in codegen prepare. The fix is to uipdate stale MBB pointers whenever a block is split during emission. llvm-svn: 115191
* Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMPEvan Cheng2010-09-291-17/+17
| | | | | | pipeline forwarding path. llvm-svn: 115098
* Removed a bunch of unnecessary target_link_libraries.Oscar Fuentes2010-09-281-2/+0
| | | | llvm-svn: 114999
* Don't try to make a vector of x86mmx; this won't work,Dale Johannesen2010-09-271-2/+4
| | | | | | and asserts. llvm-svn: 114843
* Fix for test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll crash.John Thompson2010-09-241-0/+20
| | | | llvm-svn: 114767
* Get rid of pop_macro warnings on MSVC.Michael J. Spencer2010-09-241-3/+5
| | | | llvm-svn: 114750
* Revert 114634 for now since buildbot claim it broke Clang self-hosting. I ↵Evan Cheng2010-09-231-4/+6
| | | | | | doubt it but it's possible it's exposing another bug somewhere. llvm-svn: 114681
* Fix VS 2010 build.Oscar Fuentes2010-09-231-4/+4
| | | | | | Patch by Nathan Jeffords! llvm-svn: 114661
* Follow up to r114630. Do not optimize away unconditional branch following a ↵Evan Cheng2010-09-231-6/+4
| | | | | | conditional one. llvm-svn: 114634
* SDISel should not optimize a unconditional branch following a conditional branchEvan Cheng2010-09-231-4/+5
| | | | | | | | | | | | when the unconditional branch destination is the fallthrough block. The canonicalization makes it easier to allow optimizations on DAGs to invert conditional branches. The branch folding pass (and AnalyzeBranch) will clean up the unnecessary unconditional branches later. This is one of the patches leading up to disabling codegen prepare critical edge splitting. llvm-svn: 114630
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