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* Fortify r152675 a bit. Although I'm not able to come up with a test case ↵Evan Cheng2012-03-131-3/+11
| | | | | | that would trigger the truncation case. llvm-svn: 152678
* DAG combine incorrectly optimize (i32 vextract (v4i16 load $addr), c) toEvan Cheng2012-03-131-4/+19
| | | | | | | | | (i16 load $addr+c*sizeof(i16)) and replace uses of (i32 vextract) with the i16 load. It should issue an extload instead: (i32 extload $addr+c*sizeof(i16)). rdar://11035895 llvm-svn: 152675
* Add a return type.Bill Wendling2012-03-131-1/+1
| | | | llvm-svn: 152614
* Inline the d'tor and add an anchor instead.Bill Wendling2012-03-131-1/+1
| | | | llvm-svn: 152613
* Refactor the SelectionDAG's 'dump' methods into their own .cpp file.Bill Wendling2012-03-133-633/+632
| | | | | | No functionality change. llvm-svn: 152611
* llvm::SwitchInstStepan Dyatkovskiy2012-03-111-1/+1
| | | | | | | Renamed methods caseBegin, caseEnd and caseDefault with case_begin, case_end, and case_default. Added some notes relative to case iterators. llvm-svn: 152532
* Give dagcombiner's worklist some inline capacity.Benjamin Kramer2012-03-101-3/+2
| | | | llvm-svn: 152454
* Use uint16_t to store instruction implicit uses and defs. Reduces static data.Craig Topper2012-03-082-8/+8
| | | | llvm-svn: 152301
* Taken into account Duncan's comments for r149481 dated by 2nd Feb 2012:Stepan Dyatkovskiy2012-03-081-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20120130/136146.html Implemented CaseIterator and it solves almost all described issues: we don't need to mix operand/case/successor indexing anymore. Base iterator class is implemented as a template since it may be initialized either from "const SwitchInst*" or from "SwitchInst*". ConstCaseIt is just a read-only iterator. CaseIt is read-write iterator; it allows to change case successor and case value. Usage of iterator allows totally remove resolveXXXX methods. All indexing convertions done automatically inside the iterator's getters. Main way of iterator usage looks like this: SwitchInst *SI = ... // intialize it somehow for (SwitchInst::CaseIt i = SI->caseBegin(), e = SI->caseEnd(); i != e; ++i) { BasicBlock *BB = i.getCaseSuccessor(); ConstantInt *V = i.getCaseValue(); // Do something. } If you want to convert case number to TerminatorInst successor index, just use getSuccessorIndex iterator's method. If you want initialize iterator from TerminatorInst successor index, use CaseIt::fromSuccessorIndex(...) method. There are also related changes in llvm-clients: klee and clang. llvm-svn: 152297
* misched preparation: rename core scheduler methods for consistency.Andrew Trick2012-03-076-37/+37
| | | | | | | We had half the API with one convention, half with another. Now was a good time to clean it up. llvm-svn: 152255
* misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.Andrew Trick2012-03-073-14/+22
| | | | | | | | | | | | | | | | | | | ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation. ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class. ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target. Specific changes: - Removed driver code from ScheduleDAG. clearDAG is the only interface needed. - Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls. - Added ScheduleDAGInstrs::begin()/end() public API. - Moved Sequence into the driver layer, which is specific to the scheduling algorithm. llvm-svn: 152208
* misched preparation: modularize schedule emission.Andrew Trick2012-03-072-3/+51
| | | | | | ScheduleDAG has nothing to do with how the instructions are scheduled. llvm-svn: 152206
* misched preparation: modularize schedule printing.Andrew Trick2012-03-073-0/+17
| | | | | | ScheduleDAG will not refer to the scheduled instruction sequence. llvm-svn: 152205
* misched preparation: modularize schedule verification.Andrew Trick2012-03-075-3/+22
| | | | | | ScheduleDAG will not refer to the scheduled instruction sequence. llvm-svn: 152204
* whitespaceAndrew Trick2012-03-071-5/+5
| | | | llvm-svn: 152203
* Cleanup in preparation for misched: Move DAG visualization logic.Andrew Trick2012-03-072-0/+7
| | | | | | Soon, ScheduleDAG will not refer to the BB. llvm-svn: 152177
* whitespaceAndrew Trick2012-03-071-3/+3
| | | | llvm-svn: 152175
* Cleanup: DAG building is specific to either SD or MI scheduling. Not part of ↵Andrew Trick2012-03-071-1/+1
| | | | | | the target interface. llvm-svn: 152174
* Extend r148086 to check for [r +/- reg] address mode. This fixes queens ↵Evan Cheng2012-03-061-4/+7
| | | | | | performance regression (due to increased register pressure from overly aggressive pre-inc formation). llvm-svn: 152162
* Make it possible for a target to mark FSUB as Expand. This requires ↵Owen Anderson2012-03-062-16/+39
| | | | | | providing a default expansion (FADD+FNEG), and teaching DAGCombine not to form FSUBs post-legalize if they are not legal. llvm-svn: 152079
* Fix warnings about adding a bool to a string.Bill Wendling2012-03-051-2/+2
| | | | | | Patch by Sean Silva! llvm-svn: 152042
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-042-2/+2
| | | | llvm-svn: 152001
* Fix a codegen fault in which log2 or exp2 could be dead-code eliminated even ↵James Molloy2012-03-011-2/+4
| | | | | | | | though they could have sideeffects. Only allow log2/exp2 to be converted to an intrinsic if they are declared "readnone". llvm-svn: 151807
* LegalizeIntegerTypes: Reorder operations in the "big shift by small amount" ↵Benjamin Kramer2012-02-291-4/+4
| | | | | | optimization, making the lives of later passes easier. llvm-svn: 151722
* Re-commit r151623 with fix. Only issue special no-return calls if it's a ↵Evan Cheng2012-02-285-20/+29
| | | | | | direct call. llvm-svn: 151645
* Fix off-by one in comment.Benjamin Kramer2012-02-281-1/+1
| | | | llvm-svn: 151644
* LegalizeIntegerTypes: Reenable the large shift with small amount optimization.Benjamin Kramer2012-02-281-11/+21
| | | | | | | | | | | | | To avoid problems with zero shifts when getting the bits that move between words we use a trick: first shift the by amount-1, then do another shift by one. When amount is 0 (and size 32) we first shift by 31, then by one, instead of by 32. Also fix a latent bug that emitted the low and high words in the wrong order when shifting right. Fixes PR12113. llvm-svn: 151637
* Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack ↵Daniel Dunbar2012-02-285-29/+20
| | | | | | prediction. ...", it is breaking the Clang build during the Compiler-RT part. llvm-svn: 151630
* Code cleanup following CR by Duncan.Nadav Rotem2012-02-281-5/+3
| | | | llvm-svn: 151627
* Fix a bug in the code that builds SDNodes from vector GEPs.Nadav Rotem2012-02-281-0/+4
| | | | | | | | | | | When the GEP index is a vector of pointers, the code that calculated the size of the element started from the vector type, and not the contained pointer type. As a result, instead of looking at the data element pointed by the vector, this code used the size of the vector. This works for 32bit members (on 32bit systems), but not for other types. Added code to peel the vector type and added a test. llvm-svn: 151626
* Some ARM implementaions, e.g. A-series, does return stack prediction. That is,Evan Cheng2012-02-285-20/+29
| | | | | | | | | | | | | | | | | the processor keeps a return addresses stack (RAS) which stores the address and the instruction execution state of the instruction after a function-call type branch instruction. Calling a "noreturn" function with normal call instructions (e.g. bl) can corrupt RAS and causes 100% return misprediction so LLVM should use a unconditional branch instead. i.e. mov lr, pc b _foo The "mov lr, pc" is issued in order to get proper backtrace. rdar://8979299 llvm-svn: 151623
* Don't crash when a glue node contains an internal CopyToRegHal Finkel2012-02-241-0/+3
| | | | | | | This is necessary to support the existing ppc lowering code for indirect calls. Fixes PR12071. llvm-svn: 151373
* SDAGBuilder: Remove register sets that were never read and prune dead code ↵Benjamin Kramer2012-02-241-63/+3
| | | | | | surrounding it. llvm-svn: 151364
* Turn avx insert intrinsic calls into INSERT_SUBVECTOR DAG nodes and remove ↵Pete Cooper2012-02-241-0/+15
| | | | | | duplicate patterns for selecting the intrinsics llvm-svn: 151342
* If the Address of a variable is an argument then treat the entireEric Christopher2012-02-241-3/+7
| | | | | | | | | | | variable declaration as an argument because we want that address anyhow for our debug information. This seems to fix rdar://9965111, at least we have more debug information than before and from reading the assembly it appears to be the correct location. llvm-svn: 151335
* Tabs, formatting and long lines oh my!Eric Christopher2012-02-241-4/+6
| | | | llvm-svn: 151334
* Allow an integer to be converted into an MMX type when it's used in an inlineBill Wendling2012-02-231-2/+8
| | | | | | | asm. <rdar://problem/10106006> llvm-svn: 151303
* More newline cleanups.Eric Christopher2012-02-232-4/+4
| | | | llvm-svn: 151235
* Add some handy-dandy newlines.Eric Christopher2012-02-231-2/+2
| | | | llvm-svn: 151234
* Properly emit _fltused with FastISel. Refactor to share code with SDAG.Michael J. Spencer2012-02-223-16/+29
| | | | | | Patch by Joe Groff! llvm-svn: 151183
* Make all pointers to TargetRegisterClass const since they are all pointers ↵Craig Topper2012-02-221-2/+2
| | | | | | to static data that should not be modified. llvm-svn: 151134
* Teach the DAGCombiner that certain loadext nodes followed by ANDs can be ↵James Molloy2012-02-201-0/+82
| | | | | | converted to zeroexts. llvm-svn: 150957
* Ignore the lifetime intrinsics in fast-isel.Eric Christopher2012-02-171-0/+4
| | | | llvm-svn: 150848
* Remove extraneous #include and spelling mistake introduced in r150669.James Molloy2012-02-161-2/+1
| | | | llvm-svn: 150670
* Modify the algorithm when traversing the DAGCombiner's worklist to be O(log ↵James Molloy2012-02-161-13/+36
| | | | | | N) for all operations. This fixes a horrible worst case with lots of nodes where 99% of the time was being spent in std::remove. llvm-svn: 150669
* Added hook to let targets custom lower splitting of illegal vectorsPete Cooper2012-02-151-0/+4
| | | | llvm-svn: 150550
* Fix PR12000. Some vector operations may use scalar operands with typesNadav Rotem2012-02-141-1/+5
| | | | | | | | that are greater than the vector element type. For example BUILD_VECTOR of type <1 x i1> with a constant i8 operand. This patch fixes the assertion. llvm-svn: 150477
* Rename getExceptionAddressRegister() to getExceptionPointerRegister() for ↵Lang Hames2012-02-143-3/+3
| | | | | | consistency with setExceptionPointerRegister(...). llvm-svn: 150460
* Don't reserve the R0 and R1 registers here. We don't use these registers, andBill Wendling2012-02-131-0/+6
| | | | | | | marking them as "live-in" into a BB ruins some invariants that the back-end tries to maintain. llvm-svn: 150437
* Add register mask support to ScheduleDAGRRList.Jakob Stoklund Olesen2012-02-131-11/+49
| | | | | | | | | The scheduler will sometimes check the implicit-def list on instructions to properly handle pre-colored DAG edges. Also check any register mask operands for physreg clobbers. llvm-svn: 150428
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