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* Have TargetLowering::getPICJumpTableRelocBase return a node that points to theAkira Hatanaka2012-04-091-1/+5
| | | | | | GOT if jump table uses 64-bit gp-relative relocation. llvm-svn: 154341
* Pattern match a setcc of boolean value with 0 as a truncate.Rafael Espindola2012-04-091-9/+48
| | | | llvm-svn: 154322
* Remove unnecessary type check when combining and/or/xor of swizzles. Move ↵Craig Topper2012-04-091-13/+12
| | | | | | some checks to allow better early out. llvm-svn: 154309
* Remove unnecessary 'else' on an 'if' that always returnsCraig Topper2012-04-091-1/+2
| | | | llvm-svn: 154308
* Optimize code slightly. No functionality change.Craig Topper2012-04-091-6/+7
| | | | llvm-svn: 154307
* Replace some explicit checks with asserts for conditions that should never ↵Craig Topper2012-04-091-14/+7
| | | | | | happen. llvm-svn: 154305
* Optimize code a bit. No functional change intended.Craig Topper2012-04-081-9/+9
| | | | llvm-svn: 154299
* Silence sign-compare warning.Benjamin Kramer2012-04-081-1/+1
| | | | llvm-svn: 154297
* Only have codegen turn fdiv by a constant into fmul by the reciprocalDuncan Sands2012-04-081-5/+3
| | | | | | | | when -ffast-math, i.e. don't just always do it if the reciprocal can be formed exactly. There is already an IR level transform that does that, and it does it more carefully. llvm-svn: 154296
* Simplify code that tries to do vector extracts for shuffles when the mask ↵Craig Topper2012-04-081-12/+8
| | | | | | width and the input vector widths don't match. No need to check the min and max are in range before calculating the start index. The range check after having the start index is sufficient. Also no need to check for an extract from the beginning differently. llvm-svn: 154295
* Move the TLSModel information into the TargetMachine rather than hidingChandler Carruth2012-04-081-22/+0
| | | | | | | | in TargetLowering. There was already a FIXME about this location being odd. The interface is simplified as a consequence. This will also make it easier to change TLS models when compiling with PIE. llvm-svn: 154292
* Turn avx2 vinserti128 intrinsic calls into INSERT_SUBVECTOR DAG nodes and ↵Craig Topper2012-04-071-1/+2
| | | | | | remove patterns for selecting the intrinsic. Similar was already done for avx1. llvm-svn: 154272
* Remove 'else' after 'if' that ends in return.Craig Topper2012-04-071-1/+1
| | | | llvm-svn: 154267
* 1. Remove the part of r153848 which optimizes shuffle-of-shuffle into a newNadav Rotem2012-04-071-12/+14
| | | | | | | | | | shuffle node because it could introduce new shuffle nodes that were not supported efficiently by the target. 2. Add a more restrictive shuffle-of-shuffle optimization for cases where the second shuffle reverses the transformation of the first shuffle. llvm-svn: 154266
* Convert floating point division by a constant into multiplication by theDuncan Sands2012-04-071-0/+13
| | | | | | | | reciprocal if converting to the reciprocal is exact. Do it even if inexact if -ffast-math. This substantially speeds up ac.f90 from the polyhedron benchmarks. llvm-svn: 154265
* Don't break the IV update in TLI::SimplifySetCC().Jakob Stoklund Olesen2012-04-051-15/+27
| | | | | | | | | | | | | | | | | | | LSR always tries to make the ICmp in the loop latch use the incremented induction variable. This allows the induction variable to be kept in a single register. When the induction variable limit is equal to the stride, SimplifySetCC() would break LSR's hard work by transforming: (icmp (add iv, stride), stride) --> (cmp iv, 0) This forced us to use lea for the IC update, preventing the simpler incl+cmp. <rdar://problem/7643606> <rdar://problem/11184260> llvm-svn: 154119
* Treat f16 the same as f80/f128 for the purposes of generating constants ↵Owen Anderson2012-04-051-1/+2
| | | | | | during instruction selection. llvm-svn: 154113
* f16 FREM can now be legalized by promoting to f32Pete Cooper2012-04-041-0/+1
| | | | llvm-svn: 154039
* Always compute all the bits in ComputeMaskedBits.Rafael Espindola2012-04-045-142/+85
| | | | | | | | This allows us to keep passing reduced masks to SimplifyDemandedBits, but know about all the bits if SimplifyDemandedBits fails. This allows instcombine to simplify cases like the one in the included testcase. llvm-svn: 154011
* Remove default case from switch that was already covering all cases.Craig Topper2012-04-041-1/+0
| | | | llvm-svn: 153996
* Removed useless switch for default case when switch was covering all the ↵Pete Cooper2012-04-041-1/+0
| | | | | | enum values llvm-svn: 153984
* Add VSELECT to LegalizeVectorTypes::ScalariseVectorResult. Previously it ↵Pete Cooper2012-04-032-0/+34
| | | | | | would crash if it encountered a 1 element VSELECT. Solution is slightly more complicated than just creating a SELET as we have to mask or sign extend the vector condition if it had different boolean contents from the scalar condition. Fixes <rdar://problem/11178095> llvm-svn: 153976
* Fix an issue in SimplifySetCC() specific to vector comparisons.Chad Rosier2012-04-031-2/+10
| | | | | | | | | | | When folding X == X we need to check getBooleanContents() to determine if the result is a vector of ones or a vector of negative ones. I tried creating a test case, but the problem seems to only be exposed on a much older version of clang (around r144500). rdar://10923049 llvm-svn: 153966
* Add predicates for checking whether targets have free FNEG and FABS ↵Owen Anderson2012-04-021-3/+5
| | | | | | operations, and prevent the DAGCombiner from turning them into bitwise operations if they do. llvm-svn: 153901
* Optimizing swizzles of complex shuffles may generate additional complex ↵Nadav Rotem2012-04-021-1/+9
| | | | | | | | | shuffles. Do not try to optimize swizzles of shuffles if the source shuffle has more than a single user, except when the source shuffle is also a swizzle. llvm-svn: 153864
* This commit contains a few changes that had to go in together.Nadav Rotem2012-04-011-0/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) (and also scalar_to_vector). 2. Xor/and/or are indifferent to the swizzle operation (shuffle of one src). Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A, B)) 3. Optimize swizzles of shuffles: shuff(shuff(x, y), undef) -> shuff(x, y). 4. Fix an X86ISelLowering optimization which was very bitcast-sensitive. Code which was previously compiled to this: movd (%rsi), %xmm0 movdqa .LCPI0_0(%rip), %xmm2 pshufb %xmm2, %xmm0 movd (%rdi), %xmm1 pshufb %xmm2, %xmm1 pxor %xmm0, %xmm1 pshufb .LCPI0_1(%rip), %xmm1 movd %xmm1, (%rdi) ret Now compiles to this: movl (%rsi), %eax xorl %eax, (%rdi) ret llvm-svn: 153848
* Teach CodeGen's version of computeMaskedBits to understand the range metadata.Rafael Espindola2012-03-312-7/+13
| | | | | | | | This is the CodeGen equivalent of r153747. I tested that there is not noticeable performance difference with any combination of -O0/-O2 /-g when compiling gcc as a single compilation unit. llvm-svn: 153817
* If we have a VLA that has a "use" in a metadata node that's then usedBill Wendling2012-03-301-1/+12
| | | | | | | | | | | | | | | | here but it has no other uses, then we have a problem. E.g., int foo (const int *x) { char a[*x]; return 0; } If we assign 'a' a vreg and fast isel later on has to use the selection DAG isel, it will want to copy the value to the vreg. However, there are no uses, which goes counter to what selection DAG isel expects. <rdar://problem/11134152> llvm-svn: 153705
* More debug output.Eric Christopher2012-03-281-1/+2
| | | | llvm-svn: 153571
* fix what looks like a real logic bug, found by PVS-Studio (part of PR12357)Chris Lattner2012-03-271-2/+2
| | | | llvm-svn: 153513
* Add a debug statement.Eric Christopher2012-03-261-1/+3
| | | | llvm-svn: 153428
* Add the ability to promote legal integer VAARGs. This is required for the ↵Hal Finkel2012-03-241-1/+33
| | | | | | PPC64 SVR4 ABI. llvm-svn: 153372
* Source order scheduler should not preschedule nodes with multiple uses. ↵Evan Cheng2012-03-221-7/+11
| | | | | | rdar://11096639 llvm-svn: 153270
* Assign node orders to target intrinsics which do not produce results. ↵Evan Cheng2012-03-221-0/+6
| | | | | | rdar://11096639 llvm-svn: 153269
* [fast-isel] Fold "urem x, pow2" -> "and x, pow2-1". This should fix the 271%Chad Rosier2012-03-221-0/+7
| | | | | | | | | execution-time regression for nsieve-bits on the ARMv7 -O0 -g nightly tester. This may also improve compile-time on architectures that would otherwise generate a libcall for urem (e.g., ARM) or fall back to the DAG selector. rdar://10810716 llvm-svn: 153230
* Checking a build_vector for an all-ones value.Jim Grosbach2012-03-211-5/+14
| | | | | | | | Type legalization can zero-extend the elements of the build_vector node, so, for example, we may have an <8 x i8> with i32 elements of value 255. That should return 'true' for the vector being all ones. llvm-svn: 153203
* When combining (vextract shuffle (load ), <1,u,u,u>), 0) -> (load ), add ↵Craig Topper2012-03-201-0/+1
| | | | | | users of the final load to the worklist too. Needed by changes I'm preparing to make to X86 backend. llvm-svn: 153078
* Do everything up to generating code to try to get a register forEric Christopher2012-03-201-1/+6
| | | | | | | | | | a variable. The previous code would break the debug info changing code invariant. This will regress debug info for arguments where we elide the alloca created. Fixes rdar://11066468 llvm-svn: 153074
* Untabify.Eric Christopher2012-03-201-2/+2
| | | | llvm-svn: 153073
* Add another debugging statement here.Eric Christopher2012-03-201-0/+4
| | | | llvm-svn: 153072
* Use lookUpRegForValue here instead of duplicating the code.Eric Christopher2012-03-201-9/+2
| | | | llvm-svn: 153071
* f16 FDIV can now be legalized by promoting to f32Pete Cooper2012-03-191-1/+2
| | | | llvm-svn: 153064
* Fix DAG combine which creates illegal vector shuffles. Patch by Heikki Kultala.Duncan Sands2012-03-191-0/+6
| | | | llvm-svn: 153035
* Revert r152613 (and r152614), "Inline the d'tor and add an anchor instead." ↵NAKAMURA Takumi2012-03-161-1/+1
| | | | | | | | | for workaround of g++-4.4's miscompilation. It caused MSP430DAGToDAGISel::SelectIndexedBinOp() to be miscompiled. When two ReplaceUses()'s are expanded as inline, vtable in base class is stored to latter (ISelUpdater)ISU. llvm-svn: 152877
* We actually handle AllocaInst via getRegForValue below just fine.Eric Christopher2012-03-151-1/+1
| | | | | | Part of rdar://8905263 llvm-svn: 152845
* Add some debugging output into fast isel as well.Eric Christopher2012-03-151-2/+6
| | | | llvm-svn: 152844
* Add another debug statement.Eric Christopher2012-03-151-1/+3
| | | | llvm-svn: 152843
* When optimizing certain BUILD_VECTOR nodes into other BUILD_VECTOR nodes, ↵Nadav Rotem2012-03-151-0/+4
| | | | | | add the new node into the work list because there is a potential for further optimizations. llvm-svn: 152784
* Add a xform to the DAG combiner.Bill Wendling2012-03-151-0/+17
| | | | | | | | | | | | Transform: (fsub x, (fadd x, y)) -> (fneg y) and (fsub x, (fadd y, x)) -> (fneg y) if 'unsafe math' is specified. <rdar://problem/7540295> llvm-svn: 152777
* Insert the debugging instructions in one fell-swoop so that it doesn't call theBill Wendling2012-03-141-7/+8
| | | | | | | expensive "getFirstTerminator" call. This reduces the time of compilation in PR12258 from >10 minutes to < 10 seconds. llvm-svn: 152704
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