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* Debug Info: Simplify Frame Index handling in DBG_VALUE Machine InstructionsDavid Blaikie2013-06-164-37/+43
| | | | | | | | | | | | | | | | | | | | Rather than using the full power of target-specific addressing modes in DBG_VALUEs with Frame Indicies, simply use Frame Index + Offset. This reduces the complexity of debug info handling down to two representations of values (reg+offset and frame index+offset) rather than three or four. Ideally we could ensure that frame indicies had been eliminated by the time we reached an assembly or dwarf generation, but I haven't spent the time to figure out where the FIs are leaking through into that & whether there's a good place to convert them. Some FI+offset=>reg+offset conversion is done (see PrologEpilogInserter, for example) which is necessary for some SelectionDAG assumptions about registers, I believe, but it might be possible to make this a more thorough conversion & ensure there are no remaining FIs no matter how instruction selection is performed. llvm-svn: 184066
* SelectionDAG: slightly refactor DAGCombiner::visitSELECT_CC to avoid ↵Stephen Lin2013-06-151-12/+14
| | | | | | | | redudant checks... This doesn't really effect performance due to all the relevant calls being transparent but is clearer. llvm-svn: 184027
* Introduce getSelect usage and use more getSelectCCMatt Arsenault2013-06-146-87/+90
| | | | llvm-svn: 184012
* SelectionDAG: minor fix to order of operands in comments to match the code Stephen Lin2013-06-141-3/+3
| | | | llvm-svn: 184008
* SelectionDAG: Fix incorrect condition checks in some cases of folding ↵Stephen Lin2013-06-141-16/+16
| | | | | | FADD/FMUL combinations; also improve accuracy of comments llvm-svn: 183993
* TargetLowering: Clean up method description commentsDavid Majnemer2013-06-081-3/+3
| | | | llvm-svn: 183623
* Cache the TargetLowering info object as a pointer.Bill Wendling2013-06-064-40/+39
| | | | | | | Caching it as a pointer allows us to reset it if the TargetMachine object changes. llvm-svn: 183361
* Don't cache the TargetLoweringInfo object inside of the FunctionLowering object.Bill Wendling2013-06-062-18/+19
| | | | | | | | The TargetLoweringInfo object is owned by the TargetMachine. In the future, the TargetMachine object may change, which may also change the TargetLoweringInfo object. llvm-svn: 183356
* Order CALLSEQ_START and CALLSEQ_END nodes.Andrew Trick2013-05-291-2/+4
| | | | | | | | | | | | Fixes PR16146: gdb.base__call-ar-st.exp fails after pre-RA-sched=source fixes. Patch by Xiaoyi Guo! This also fixes an unsupported dbg.value test case. Codegen was previously incorrect but the test was passing by luck. llvm-svn: 182885
* Simplify code. No functionality change.Benjamin Kramer2013-05-281-3/+2
| | | | llvm-svn: 182779
* Remove double semicolons.Benjamin Kramer2013-05-283-62/+62
| | | | llvm-svn: 182778
* Convert sqrt functions into sqrt instructions when -ffast-math is in effect.Preston Gurd2013-05-271-0/+3
| | | | | | | | | | | | When -ffast-math is in effect (on Linux, at least), clang defines __FINITE_MATH_ONLY__ > 0 when including <math.h>. This causes the preprocessor to include <bits/math-finite.h>, which renames the sqrt functions. For instance, "sqrt" is renamed as "__sqrt_finite". This patch adds the 3 new names in such a way that they will be treated as equivalent to their respective original names. llvm-svn: 182739
* Fix PR16143: Insert DEBUG_VALUE before terminator.Andrew Trick2013-05-261-1/+1
| | | | llvm-svn: 182717
* Track IR ordering of SelectionDAG nodes 3/4.Andrew Trick2013-05-258-159/+14
| | | | | | | Remove the old IR ordering mechanism and switch to new one. Fix unit test failures. llvm-svn: 182704
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-2515-1209/+1213
| | | | | | | Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
* Track IR ordering of SelectionDAG nodes 1/4.Andrew Trick2013-05-252-7/+15
| | | | | | | | Use a field in the SelectionDAGNode object to track its IR ordering. This adds fields and utility classes without changing existing interfaces or functionality. llvm-svn: 182701
* Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.Michael J. Spencer2013-05-242-3/+3
| | | | llvm-svn: 182680
* Unify formatting of debug output.Adrian Prantl2013-05-222-3/+3
| | | | llvm-svn: 182495
* Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen.Justin Holewinski2013-05-211-0/+5
| | | | | | | | | | The intrinsic calls are dropped, but the annotated value is propagated. Fixes PR 15253 Original patch by Zeng Bin! llvm-svn: 182387
* DAGCombine: Avoid an edge case where it tried to create an i0 type for (x & ↵Benjamin Kramer2013-05-211-1/+2
| | | | | | | | 0) == 0. Fixes PR16083. llvm-svn: 182357
* Add LLVMContext argument to getSetCCResultTypeMatt Arsenault2013-05-189-60/+80
| | | | llvm-svn: 182180
* Replace redundant codeMatt Arsenault2013-05-171-7/+2
| | | | | | | Use EVT::changeExtendedVectorElementTypeToInteger instead of doing the same thing that it does llvm-svn: 182165
* Add missing -*- C++ -*- to headersMatt Arsenault2013-05-171-1/+1
| | | | llvm-svn: 182164
* Generate debug info for by-value struct args even if they are not used.Adrian Prantl2013-05-161-1/+7
| | | | | | radar://problem/13865940 llvm-svn: 182062
* DAGCombine: Also shrink eq compares where the constant is exactly as large ↵Benjamin Kramer2013-05-161-1/+1
| | | | | | | | | | | | as the smaller type. if ((x & 255) == 255) before: movzbl %al, %eax cmpl $255, %eax after: cmpb $-1, %al llvm-svn: 182038
* Fix legalization of SETCC with promoted integer intrinsicsHal Finkel2013-05-151-2/+13
| | | | | | | | | | | | | | | | | | If the input operands to SETCC are promoted, we need to make sure that we either use the promoted form of both operands (or neither); a mixture is not allowed. This can happen, for example, if a target has a custom promoted i1-returning intrinsic (where i1 is not a legal type). In this case, we need to use the promoted form of both operands. This change only augments the behavior of the existing logic in the case where the input types (which may or may not have already been legalized) disagree, and should not affect existing target code because this case would otherwise cause an assert in the SETCC operand promotion code. This will be covered by (essentially all of the) tests for the new PPCCTRLoops infrastructure. llvm-svn: 181926
* Remove redundant variable introduced by r181682.Bob Wilson2013-05-131-1/+0
| | | | llvm-svn: 181721
* Fix PR15950 A bug in DAG Combiner about undef maskHao Liu2013-05-131-10/+25
| | | | llvm-svn: 181682
* DAGCombiner: Generate a correct constant for vector types when folding (xor ↵Benjamin Kramer2013-05-101-2/+1
| | | | | | | | (and)) into (and (not)). PR15948. llvm-svn: 181597
* Teach SelectionDAG to constant fold all-constant FMA nodes the same way that ↵Owen Anderson2013-05-091-0/+15
| | | | | | it constant folds FADD, FMUL, etc. llvm-svn: 181555
* DAGCombiner: Simplify inverted bit testsDavid Majnemer2013-05-081-0/+9
| | | | | | | | Fold (xor (and x, y), y) -> (and (not x), y) This removes an opportunity for a constant to appear twice. llvm-svn: 181395
* Fix vselect when getSetCCResultType returns a different type from the operandsMatt Arsenault2013-05-071-3/+8
| | | | llvm-svn: 181348
* Fix slightly too aggressive conact_vector optimization.Michael Kuperstein2013-05-061-0/+6
| | | | | | (Would sometimes optimize away conacts used to extend a vector with undef values) llvm-svn: 181186
* Add ArrayRef constructor from None, and do the cleanups that this ↵Dmitri Gribenko2013-05-051-2/+2
| | | | | | | | constructor enables Patch by Robert Wilhelm. llvm-svn: 181138
* [inline asm] Return an undef SDValue of the expected value type, rather thanChad Rosier2013-05-011-1/+1
| | | | | | | | | report a fatal error. This allows us to continue processing the translation unit. Test case to come on the clang side because we need an inline asm diagnostics handler in place. rdar://13446483 llvm-svn: 180873
* Optimize away nop CONCAT_VECTOR nodes.Nadav Rotem2013-05-011-0/+39
| | | | | | | | | Optimize CONCAT_VECTOR nodes that merge EXTRACT_SUBVECTOR values that extract from the same vector. rdar://13402653 PR15866 llvm-svn: 180871
* Only pass 'returned' to target-specific lowering code when the value of ↵Stephen Lin2013-04-301-24/+42
| | | | | | entire register is guaranteed to be preserved. llvm-svn: 180825
* Temporarily revert "Change the informal convention of DBG_VALUE so that we ↵Adrian Prantl2013-04-304-27/+18
| | | | | | | | | | can express a" because it breaks some buildbots. This reverts commit 180816. llvm-svn: 180819
* Change the informal convention of DBG_VALUE so that we can express aAdrian Prantl2013-04-304-18/+27
| | | | | | | | | | | | register-indirect address with an offset of 0. It used to be that a DBG_VALUE is a register-indirect value if the offset (operand 1) is nonzero. The new convention is that a DBG_VALUE is register-indirect if the first operand is a register and the second operand is an immediate. For plain registers use the combination reg, reg. rdar://problem/13658587 llvm-svn: 180816
* Re-write the address propagation code for pre-indexed loads/stores to take ↵Silviu Baranga2013-04-261-14/+29
| | | | | | into account some previously misssed cases (PRE_DEC addressing mode, the offset and base address are swapped, etc). This should fix PR15581. llvm-svn: 180609
* DAGCombiner: Canonicalize vector integer abs in the same way we do it for ↵Benjamin Kramer2013-04-261-0/+42
| | | | | | | | | | scalars. This already helps SSE2 x86 a lot because it lacks an efficient way to represent a vector select. The long term goal is to enable the backend to match a canonicalized pattern into a single instruction (e.g. vabs or pabs). llvm-svn: 180597
* Fix constant folding for one lane vector types. Constant folding one lane ↵Silviu Baranga2013-04-251-1/+1
| | | | | | vector types not returns a vector instead of a scalar. llvm-svn: 180254
* [inline asm] Fix a crasher for an invalid value type/register class.Chad Rosier2013-04-241-4/+11
| | | | | | rdar://13731657 llvm-svn: 180226
* DAGCombine should not aggressively fold SEXT(VSETCC(...)) into a wider ↵Owen Anderson2013-04-231-1/+3
| | | | | | | | | VSETCC without first checking the target's vector boolean contents. This exposed an issue with PowerPC AltiVec where it appears it was setting the wrong vector boolean contents. The included change fixes the PowerPC tests, and was OK'd by Hal. llvm-svn: 180129
* Legalize vector truncates by parts rather than just splitting.Jim Grosbach2013-04-212-1/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than just splitting the input type and hoping for the best, apply a bit more cleverness. Just splitting the types until the source is legal often leads to an illegal result time, which is then widened and a scalarization step is introduced which leads to truly horrible code generation. With the loop vectorizer, these sorts of operations are much more common, and so it's worth extra effort to do them well. Add a legalization hook for the operands of a TRUNCATE node, which will be encountered after the result type has been legalized, but if the operand type is still illegal. If simple splitting of both types ends up with the result type of each half still being legal, just do that (v16i16 -> v16i8 on ARM, for example). If, however, that would result in an illegal result type (v8i32 -> v8i8 on ARM, for example), we can get more clever with power-two vectors. Specifically, split the input type, but also widen the result element size, then concatenate the halves and truncate again. For example on ARM, To perform a "%res = v8i8 trunc v8i32 %in" we transform to: %inlo = v4i32 extract_subvector %in, 0 %inhi = v4i32 extract_subvector %in, 4 %lo16 = v4i16 trunc v4i32 %inlo %hi16 = v4i16 trunc v4i32 %inhi %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16 %res = v8i8 trunc v8i16 %in16 This allows instruction selection to generate three VMOVN instructions instead of a sequences of moves, stores and loads. Update the ARMTargetTransformInfo to take this improved legalization into account. Consider the simplified IR: define <16 x i8> @test1(<16 x i32>* %ap) { %a = load <16 x i32>* %ap %tmp = trunc <16 x i32> %a to <16 x i8> ret <16 x i8> %tmp } define <8 x i8> @test2(<8 x i32>* %ap) { %a = load <8 x i32>* %ap %tmp = trunc <8 x i32> %a to <8 x i8> ret <8 x i8> %tmp } Previously, we would generate the truly hideous: .syntax unified .section __TEXT,__text,regular,pure_instructions .globl _test1 .align 2 _test1: @ @test1 @ BB#0: push {r7} mov r7, sp sub sp, sp, #20 bic sp, sp, #7 add r1, r0, #48 add r2, r0, #32 vld1.64 {d24, d25}, [r0:128] vld1.64 {d16, d17}, [r1:128] vld1.64 {d18, d19}, [r2:128] add r1, r0, #16 vmovn.i32 d22, q8 vld1.64 {d16, d17}, [r1:128] vmovn.i32 d20, q9 vmovn.i32 d18, q12 vmov.u16 r0, d22[3] strb r0, [sp, #15] vmov.u16 r0, d22[2] strb r0, [sp, #14] vmov.u16 r0, d22[1] strb r0, [sp, #13] vmov.u16 r0, d22[0] vmovn.i32 d16, q8 strb r0, [sp, #12] vmov.u16 r0, d20[3] strb r0, [sp, #11] vmov.u16 r0, d20[2] strb r0, [sp, #10] vmov.u16 r0, d20[1] strb r0, [sp, #9] vmov.u16 r0, d20[0] strb r0, [sp, #8] vmov.u16 r0, d18[3] strb r0, [sp, #3] vmov.u16 r0, d18[2] strb r0, [sp, #2] vmov.u16 r0, d18[1] strb r0, [sp, #1] vmov.u16 r0, d18[0] strb r0, [sp] vmov.u16 r0, d16[3] strb r0, [sp, #7] vmov.u16 r0, d16[2] strb r0, [sp, #6] vmov.u16 r0, d16[1] strb r0, [sp, #5] vmov.u16 r0, d16[0] strb r0, [sp, #4] vldmia sp, {d16, d17} vmov r0, r1, d16 vmov r2, r3, d17 mov sp, r7 pop {r7} bx lr .globl _test2 .align 2 _test2: @ @test2 @ BB#0: push {r7} mov r7, sp sub sp, sp, #12 bic sp, sp, #7 vld1.64 {d16, d17}, [r0:128] add r0, r0, #16 vld1.64 {d20, d21}, [r0:128] vmovn.i32 d18, q8 vmov.u16 r0, d18[3] vmovn.i32 d16, q10 strb r0, [sp, #3] vmov.u16 r0, d18[2] strb r0, [sp, #2] vmov.u16 r0, d18[1] strb r0, [sp, #1] vmov.u16 r0, d18[0] strb r0, [sp] vmov.u16 r0, d16[3] strb r0, [sp, #7] vmov.u16 r0, d16[2] strb r0, [sp, #6] vmov.u16 r0, d16[1] strb r0, [sp, #5] vmov.u16 r0, d16[0] strb r0, [sp, #4] ldm sp, {r0, r1} mov sp, r7 pop {r7} bx lr Now, however, we generate the much more straightforward: .syntax unified .section __TEXT,__text,regular,pure_instructions .globl _test1 .align 2 _test1: @ @test1 @ BB#0: add r1, r0, #48 add r2, r0, #32 vld1.64 {d20, d21}, [r0:128] vld1.64 {d16, d17}, [r1:128] add r1, r0, #16 vld1.64 {d18, d19}, [r2:128] vld1.64 {d22, d23}, [r1:128] vmovn.i32 d17, q8 vmovn.i32 d16, q9 vmovn.i32 d18, q10 vmovn.i32 d19, q11 vmovn.i16 d17, q8 vmovn.i16 d16, q9 vmov r0, r1, d16 vmov r2, r3, d17 bx lr .globl _test2 .align 2 _test2: @ @test2 @ BB#0: vld1.64 {d16, d17}, [r0:128] add r0, r0, #16 vld1.64 {d18, d19}, [r0:128] vmovn.i32 d16, q8 vmovn.i32 d17, q9 vmovn.i16 d16, q8 vmov r0, r1, d16 bx lr llvm-svn: 179989
* Tidy up comment grammar.Jim Grosbach2013-04-211-2/+2
| | | | llvm-svn: 179986
* Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.Tim Northover2013-04-205-71/+1
| | | | llvm-svn: 179939
* Add CodeGen support for functions that always return arguments via a new ↵Stephen Lin2013-04-201-7/+11
| | | | | | parameter attribute 'returned', which is taken advantage of in target-independent tail call opportunity detection and in ARM call lowering (when placed on an integral first parameter). llvm-svn: 179925
* Simplify the code in FastISel::tryToFoldLoad, add an assertion and fix a ↵Eli Bendersky2013-04-191-17/+10
| | | | | | comment. llvm-svn: 179908
* Move TryToFoldFastISelLoad to FastISel, where it belongs. In general, I'mEli Bendersky2013-04-192-79/+66
| | | | | | | trying to move as much FastISel logic as possible out of the main path in SelectionDAGISel - intermixing them just adds confusion. llvm-svn: 179902
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