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* Non-fast-isel followup to 129634; correctly handle branches controlledStuart Hastings2011-05-121-2/+9
| | | | | | | | | | | | | by non-CMP expressions. The executable test case (129821) would test this as well, if we had an "-O0 -disable-arm-fast-isel" LLVM-GCC tester. Alas, the ARM assembly would be very difficult to check with FileCheck. The thumb2-cbnz.ll test is affected; it generates larger code (tst.w vs. cmp #0), but I believe the new version is correct. rdar://problem/9298790 llvm-svn: 131261
* Fixes a bug in the DAGCombiner. LoadSDNodes have two values (data, chain).Nadav Rotem2011-05-111-1/+1
| | | | | | | | If there is a store after the load node, then there is a chain, which means that there is another user. Thus, asking hasOneUser would fail. Instead we ask hasNUsesOfValue on the 'data' value. llvm-svn: 131183
* Give the 'eh.sjlj.dispatchsetup' intrinsic call the value coming from the setjmpBill Wendling2011-05-111-1/+1
| | | | | | | | intrinsic call. This prevents it from being reordered so that it appears *before* the setjmp intrinsic (thus making it completely useless). <rdar://problem/9409683> llvm-svn: 131174
* Disable my little CopyToReg argument hack with fast-isel. ↵Eli Friedman2011-05-101-2/+3
| | | | | | rdar://problem/9413587 . llvm-svn: 131156
* Correctly walk through nested and adjacent CALLSEQ_START nodes. NoStuart Hastings2011-05-101-1/+2
| | | | | | | test case; I've only seen this on a release branch, and I can't get it to reproduce on trunk. rdar://problem/7662569 llvm-svn: 131152
* Look through struct wrapped types for inline asm statments.Eric Christopher2011-05-092-0/+12
| | | | | | Patch by Evan Cheng. llvm-svn: 131093
* Indent properly, no functionality change.Duncan Sands2011-05-091-12/+12
| | | | llvm-svn: 131082
* 80 col violations.Evan Cheng2011-05-061-3/+7
| | | | llvm-svn: 131015
* Make the logic for determining function alignment more explicit. No ↵Eli Friedman2011-05-061-0/+2
| | | | | | functionality change. llvm-svn: 131012
* Use array_lengthof. No functional change.Eli Friedman2011-05-061-3/+1
| | | | llvm-svn: 131008
* Allow FastISel of three-register-operand instructions.Owen Anderson2011-05-051-0/+24
| | | | llvm-svn: 130934
* Avoid extra vreg copies for arguments passed in registers. Specifically, ↵Eli Friedman2011-05-052-38/+44
| | | | | | this can make MachineCSE more effective in some cases (especially in small functions). PR8361 / part of rdar://problem/8259436 . llvm-svn: 130928
* Small syntax cleanup; we don't need to #define constants in C++. No ↵Eli Friedman2011-05-051-3/+3
| | | | | | functionality change intended. llvm-svn: 130926
* Other parts of the SelectionDAG framework assume that targets use their ↵Owen Anderson2011-05-021-1/+1
| | | | | | pointer type for vector indices. Make the vector unrolling code respect that. llvm-svn: 130733
* Make FastEmit_ri_ try a bit harder to succeed for supported operations; ↵Eli Friedman2011-04-291-2/+7
| | | | | | FastEmit_i can fail for non-Thumb2 ARM. Makes ARMSimplifyAddress work correctly, and reduces the number of fast-isel bailouts on non-Thumb ARM. llvm-svn: 130560
* Fix a silly mistake in r130338.Eli Friedman2011-04-281-1/+1
| | | | llvm-svn: 130360
* Make the fast-isel code for literal 0.0 a bit shorter/faster, since 0.0 is ↵Eli Friedman2011-04-271-2/+6
| | | | | | common. rdar://problem/9303592 . llvm-svn: 130338
* Remove unused function.Eli Friedman2011-04-271-47/+0
| | | | llvm-svn: 130337
* Be careful about scheduling nodes above previous calls. It increase usages ofEvan Cheng2011-04-262-1/+61
| | | | | | | | | | | | more callee-saved registers and introduce copies. Only allows it if scheduling a node above calls would end up lessen register pressure. Call operands also has added ABI restrictions for register allocation, so be extra careful with hoisting them above calls. rdar://9329627 llvm-svn: 130245
* Fast-isel support for simple inline asms.Dan Gohman2011-04-261-10/+31
| | | | llvm-svn: 130205
* Fix typoEvan Cheng2011-04-261-1/+1
| | | | llvm-svn: 130190
* A dbg.declare may not be in entry block, even if it is referring to an ↵Devang Patel2011-04-251-4/+0
| | | | | | incoming argument. However, It is appropriate to emit DBG_VALUE referring to this incoming argument in entry block in MachineFunction. llvm-svn: 130129
* Remove unused STL header includes.Jay Foad2011-04-231-1/+0
| | | | llvm-svn: 130068
* Teach FastISel to deal with instructions that have two immediate operands.Owen Anderson2011-04-221-10/+27
| | | | llvm-svn: 130033
* Recommit the fix for rdar://9289512 with a couple tweaks toChris Lattner2011-04-221-17/+54
| | | | | | | | | | | fix bugs exposed by the gcc dejagnu testsuite: 1. The load may actually be used by a dead instruction, which would cause an assert. 2. The load may not be used by the current chain of instructions, and we could move it past a side-effecting instruction. Change how we process uses to define the problem away. llvm-svn: 130018
* DAGCombine: fold "(zext x) == C" into "x == (trunc C)" if the trunc is lossless.Benjamin Kramer2011-04-221-0/+36
| | | | | | | | | | | | On x86 this allows to fold a load into the cmp, greatly reducing register pressure. movzbl (%rdi), %eax cmpl $47, %eax -> cmpb $47, (%rdi) This shaves 8k off gcc.o on i386. I'll leave applying the patch in README.txt to Chris :) llvm-svn: 130005
* Revert r1296656, "Fix rdar://9289512 - not folding load into compare at -O0...",Daniel Dunbar2011-04-211-41/+15
| | | | | | which broke a couple GCC test suite tests at -O0. llvm-svn: 129914
* Rewrite the expander for umulo/smulo to remember to sign extend the inputEric Christopher2011-04-201-10/+58
| | | | | | | | | manually and pass all (now) 4 arguments to the mul libcall. Add a new ExpandLibCall for just this (copied gratuitously from type legalization). Fixes rdar://9292577 llvm-svn: 129842
* Delete unnecessary variable. <rdar://problem/7662569>Stuart Hastings2011-04-191-11/+4
| | | | llvm-svn: 129796
* SelectBasicBlock is rather slow even when it doesn't do anything; skip theEli Friedman2011-04-191-5/+7
| | | | | | unnecessary work where possible. llvm-svn: 129763
* Support nested CALLSEQ_BEGIN/END; necessary for ARM byval support. ↵Stuart Hastings2011-04-191-42/+56
| | | | | | <rdar://problem/7662569> llvm-svn: 129761
* Implement support for x86 fastisel of small fixed-sized memcpys, which are ↵Chris Lattner2011-04-191-52/+44
| | | | | | | | | generated en-mass for C++ PODs. On my c++ test file, this cuts the fast isel rejects by 10x and shrinks the generated .s file by 5% llvm-svn: 129755
* while we're at it, handle 'sdiv exact' of a power of 2 also,Chris Lattner2011-04-181-0/+8
| | | | | | this fixes a few rejects on c++ iterator loops. llvm-svn: 129694
* fix rdar://9297011 - udiv by power of two causing fast-isel rejectsChris Lattner2011-04-181-0/+4
| | | | llvm-svn: 129693
* 1. merge fast-isel-shift-imm.ll into fast-isel-x86-64.llChris Lattner2011-04-171-18/+30
| | | | | | | | | | 2. implement rdar://9289501 - fast isel should fold trivial multiplies to shifts 3. teach tblgen to handle shift immediates that are different sizes than the shifted operands, eliminating some code from the X86 fast isel backend. 4. Have FastISel::SelectBinaryOp use (the poorly named) FastEmit_ri_ function instead of FastEmit_ri to simplify code. llvm-svn: 129666
* fix an oversight which caused us to compile the testcase (and otherChris Lattner2011-04-171-5/+3
| | | | | | | | | | | | | | | | | | | less trivial things) into a dummy lea. Before we generated: _test: ## @test movq _G@GOTPCREL(%rip), %rax leaq (%rax), %rax ret now we produce: _test: ## @test movq _G@GOTPCREL(%rip), %rax ret This is part of rdar://9289558 llvm-svn: 129662
* Fix rdar://9289512 - not folding load into compare at -O0Chris Lattner2011-04-171-15/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | The basic issue here is that bottom-up isel is matching the branch and compare, and was failing to fold the load into the branch/compare combo. Fixing this (by allowing folding into any instruction of a sequence that is selected) allows us to produce things like: cmpb $0, 52(%rax) je LBB4_2 instead of: movb 52(%rax), %cl cmpb $0, %cl je LBB4_2 This makes the generated -O0 code run a bit faster, but also speeds up compile time by putting less pressure on the register allocator and generating less code. This was one of the biggest classes of missing load folding. Implementing this shrinks 176.gcc's c-decl.s (as a random example) by about 4% in (verbose-asm) line count. llvm-svn: 129656
* split a complex predicate out to a helper function. Simplify two for loops,Chris Lattner2011-04-171-10/+16
| | | | | | | which don't need to check for falling off the end of a block *and* end of phi nodes, since terminators are never phis. llvm-svn: 129655
* fix rdar://9289583 - fast isel should handle non-canonical commutative binopsChris Lattner2011-04-171-4/+23
| | | | | | | | | | allowing us to fold the immediate into the 'and' in this case: int test1(int i) { return 8&i; } llvm-svn: 129653
* PR9055: extend the fix to PR4050 (r70179) to apply to zext and anyext.Eli Friedman2011-04-161-2/+2
| | | | | | | Returning a new node makes the code try to replace the old node, which in the included testcase is killed by CSE. llvm-svn: 129650
* Fix divmod libcall lowering. Convert to {S|U}DIVREM first and then expand ↵Evan Cheng2011-04-161-71/+65
| | | | | | the node to a libcall. rdar://9280991 llvm-svn: 129633
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-155-10/+9
| | | | | | Luis Felipe Strano Moraes! llvm-svn: 129558
* Fix another instance of the DAG combiner not using the correct type for the ↵Owen Anderson2011-04-141-3/+5
| | | | | | RHS of a shift. llvm-svn: 129522
* In the pre-RA scheduler, maintain cmp+br proximity.Andrew Trick2011-04-142-13/+61
| | | | | | | | | | | | | | | | | | | | | | | | This is done by pushing physical register definitions close to their use, which happens to handle flag definitions if they're not glued to the branch. This seems to be generally a good thing though, so I didn't need to add a target hook yet. The primary motivation is to generate code closer to what people expect and rule out missed opportunity from enabling macro-op fusion. As a side benefit, we get several 2-5% gains on x86 benchmarks. There is one regression: SingleSource/Benchmarks/Shootout/lists slows down be -10%. But this is an independent scheduler bug that will be tracked separately. See rdar://problem/9283108. Incidentally, pre-RA scheduling is only half the solution. Fixing the later passes is tracked by: <rdar://problem/8932804> [pre-RA-sched] on x86, attempt to schedule CMP/TEST adjacent with condition jump Fixes: <rdar://problem/9262453> Scheduler unnecessary break of cmp/jump fusion llvm-svn: 129508
* sink a call into its only use.Chris Lattner2011-04-141-2/+1
| | | | llvm-svn: 129503
* During post-legalization DAG combining, be careful to only create shifts ↵Owen Anderson2011-04-131-1/+8
| | | | | | where the RHS is of the legal type for the new operation. llvm-svn: 129484
* Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor ↵Andrew Trick2011-04-132-156/+190
| | | | | | | | | | | | | | | | | | | | | latency. Additional fixes: Do something reasonable for subtargets with generic itineraries by handle node latency the same as for an empty itinerary. Now nodes default to unit latency unless an itinerary explicitly specifies a zero cycle stage or it is a TokenFactor chain. Original fixes: UnitsSharePred was a source of randomness in the scheduler: node priority depended on the queue data structure. I rewrote the recent VRegCycle heuristics to completely replace the old heuristic without any randomness. To make the ndoe latency adjustments work, I also needed to do something a little more reasonable with TokenFactor. I gave it zero latency to its consumers and always schedule it as low as possible. llvm-svn: 129421
* Revert 129383. It causes some targets to hit a scheduler assert.Andrew Trick2011-04-122-184/+157
| | | | llvm-svn: 129385
* PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency.Andrew Trick2011-04-122-157/+184
| | | | | | | | | | | | UnitsSharePred was a source of randomness in the scheduler: node priority depended on the queue data structure. I rewrote the recent VRegCycle heuristics to completely replace the old heuristic without any randomness. To make these heuristic adjustments to node latency work, I also needed to do something a little more reasonable with TokenFactor. I gave it zero latency to its consumers and always schedule it as low as possible. llvm-svn: 129383
* Don't include Operator.h from InstrTypes.h.Jay Foad2011-04-111-0/+1
| | | | llvm-svn: 129271
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