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* Add "inreg" field to CallSDNode (doesn't increaseDale Johannesen2008-09-265-17/+24
| | | | | | | | | its size). Adjust various lowering functions to pass this info through from CallInst. Use it to implement sseregparm returns on X86. Remove X86_ssecall calling convention. llvm-svn: 56677
* Large mechanical patch.Devang Patel2008-09-252-20/+20
| | | | | | | | | | | | | | | s/ParamAttr/Attribute/g s/PAList/AttrList/g s/FnAttributeWithIndex/AttributeWithIndex/g s/FnAttr/Attribute/g This sets the stage - to implement function notes as function attributes and - to distinguish between function attributes and return value attributes. This requires corresponding changes in llvm-gcc and clang. llvm-svn: 56622
* Accept 'inreg' attribute on x86 functions asDale Johannesen2008-09-251-2/+7
| | | | | | | | meaning sse_regparm (i.e. float/double values go in XMM0 instead of ST0). Update documentation to reflect reality. llvm-svn: 56619
* Support for i1 XOR in FastISel. It is actually safe becauseDan Gohman2008-09-251-2/+3
| | | | | | i1 operands are assumed to already by zero-extended. llvm-svn: 56615
* Don't print fast-isel debug messages by default. Thanks Chris!Dan Gohman2008-09-251-3/+6
| | | | llvm-svn: 56614
* Don't forget the newline in debug output.Dan Gohman2008-09-251-1/+1
| | | | llvm-svn: 56613
* FastISel support for debug info.Dan Gohman2008-09-253-3/+117
| | | | llvm-svn: 56610
* bug 2812: Segmentation fault on a big emdiam processor.Richard Pennington2008-09-251-1/+1
| | | | llvm-svn: 56609
* Fix a recent fast-isel coverage regression - don't bail out beforeDan Gohman2008-09-251-3/+4
| | | | | | giving the target a chance to materialize constants. llvm-svn: 56605
* Enable DeadMachineInstructionElim when Fast-ISel is enabled.Dan Gohman2008-09-251-3/+0
| | | | llvm-svn: 56604
* <rdar://problem/6234798> Assertion failed: ↵Evan Cheng2008-09-251-2/+5
| | | | | | (!OpInfo.AssignedRegs.Regs.empty() && "Couldn't allocate input reg!") llvm-svn: 56597
* Remove SelectionDag early allocation of registersDale Johannesen2008-09-242-41/+10
| | | | | | | for earlyclobbers. Teach Local RA about earlyclobber, and add some tests for it. llvm-svn: 56592
* Reapplying r56550Bill Wendling2008-09-241-13/+13
| | | | llvm-svn: 56553
* Forgot this part with my last patch. Sorry about the breakage.Bill Wendling2008-09-241-27/+38
| | | | llvm-svn: 56552
* Temporarily revert r56550 until missing commit can be added.Eric Christopher2008-09-241-13/+13
| | | | llvm-svn: 56551
* Refactor the constant folding code into it's own function. And call it from bothBill Wendling2008-09-241-13/+13
| | | | | | | | | | the SelectionDAG and DAGCombiner code. The only functionality change is that now the DAG combiner is performing the constant folding for these operations instead of being a no-op. This is *not* in response to a bug, so there isn't a testcase. llvm-svn: 56550
* Next round of earlyclobber handling. Approach theDale Johannesen2008-09-243-42/+17
| | | | | | | | | | RA problem by expanding the live interval of an earlyclobber def back one slot. Remove overlap-earlyclobber throughout. Remove earlyclobber bits and their handling from live internals. llvm-svn: 56539
* Properly handle 'm' inline asm constraints. If a GV is being selected for ↵Evan Cheng2008-09-242-5/+25
| | | | | | the addressing mode, it requires the same logic for PIC relative addressing, etc. llvm-svn: 56526
* s/ParameterAttributes/Attributes/gDevang Patel2008-09-232-2/+0
| | | | llvm-svn: 56513
* Arrange for FastISel code to have access to the MachineModuleInfoDan Gohman2008-09-232-5/+10
| | | | | | object. This will be needed to support debug info. llvm-svn: 56508
* Replace the LiveRegs SmallSet with a simple counter that keepsDan Gohman2008-09-232-23/+29
| | | | | | | track of the number of live registers, which is all the set was being used for. llvm-svn: 56498
* Fix the alignment of loads from constant pool entries when theDan Gohman2008-09-222-1/+7
| | | | | | | load address has an offset from the base of the constant pool entry. llvm-svn: 56479
* Make log, log2, log10, exp, exp2 use Expand byDale Johannesen2008-09-221-0/+12
| | | | | | default. llvm-svn: 56471
* Per review feedback: Only performEvan Cheng2008-09-221-39/+27
| | | | | | | (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), c)) etc. when both "trunc" and "and" have single uses. llvm-svn: 56452
* Initial support for the CMake build system.Oscar Fuentes2008-09-221-0/+21
| | | | llvm-svn: 56419
* Add helper function to get a 32-bit floating point constant. No ↵Bill Wendling2008-09-221-189/+106
| | | | | | functionality change. llvm-svn: 56418
* don't print GlobalAddressSDNode's with an offset of zero as "foo0".Chris Lattner2008-09-211-5/+6
| | | | llvm-svn: 56399
* Refactor X86SelectConstAddr, folding it into X86SelectAddress. ThisDan Gohman2008-09-191-21/+15
| | | | | | | results in better code for globals. Also, unbreak the local CSE for GlobalValue stub loads. llvm-svn: 56371
* Add a new "fast" scheduler. This is currently basically just aDan Gohman2008-09-181-0/+654
| | | | | | | | | | | | | | | | copy of the BURRList scheduler, but with several parts ripped out, such as backtracking, online topological sort maintenance (needed by backtracking), the priority queue, and Sethi-Ullman number computation and maintenance (needed by the priority queue). As a result of all this, it generates somewhat lower quality code, but that's its tradeoff for running about 30% faster than list-burr in -fast mode in many cases. This is somewhat experimental. Moving forward, major pieces of this can be refactored with pieces in common with ScheduleDAGRRList.cpp. llvm-svn: 56307
* Add a bit to mark operands of asm's that conflictDale Johannesen2008-09-173-20/+44
| | | | | | | | | with an earlyclobber operand elsewhere. Propagate this bit and the earlyclobber bit through SDISel. Change linear-scan RA not to allocate regs in a way that conflicts with an earlyclobber. See also comments. llvm-svn: 56290
* Don't worry about clobbering physical register defs that aren't used.Dan Gohman2008-09-171-0/+2
| | | | llvm-svn: 56281
* When converting a CopyFromReg to a copy instruction, use the register class ↵Evan Cheng2008-09-161-5/+24
| | | | | | of its uses to determine the right destination register class of the copy. This is important for targets where a physical register may belong to multiple register classes. llvm-svn: 56258
* Change SelectionDAG::getConstantPool to always set the alignment of theDan Gohman2008-09-162-7/+20
| | | | | | | | | | | | | | | | | | | | ConstantPoolSDNode, using the target's preferred alignment for the constant type. In LegalizeDAG, when performing loads from the constant pool, the ConstantPoolSDNode's alignment is used in the calls to getLoad and getExtLoad. This change prevents SelectionDAG::getLoad/getExtLoad from incorrectly choosing the ABI alignment for constant pool loads when Alignment == 0. The incorrect alignment is only a performance issue when ABI alignment does not equal preferred alignment (i.e., on x86 it was generating MOVUPS instead of MOVAPS for v4f32 constant loads when the default ABI alignment for 128bit vectors is forced to 1 byte.) Patch by Paul Redmond! llvm-svn: 56253
* Reverting r56249. On further investigation, this functionality isn't needed.Bill Wendling2008-09-166-59/+45
| | | | | | Apologies for the thrashing. llvm-svn: 56251
* Include the alignment value when displaying ConstantPoolSDNodes.Dan Gohman2008-09-161-0/+1
| | | | llvm-svn: 56250
* - Change "ExternalSymbolSDNode" to "SymbolSDNode".Bill Wendling2008-09-166-45/+59
| | | | | | | | | | - Add linkage to SymbolSDNode (default to external). - Change ISD::ExternalSymbol to ISD::Symbol. - Change ISD::TargetExternalSymbol to ISD::TargetSymbol These changes pave the way to allowing SymbolSDNodes with non-external linkage. llvm-svn: 56249
* Don't take the time to CheckDAGForTailCallsAndFixThem when tail callsDan Gohman2008-09-162-4/+10
| | | | | | | are not enabled. Instead just omit the tail call flag when calls are created. llvm-svn: 56235
* Re-enable SelectionDAG CSE for calls. It matters in the case ofDan Gohman2008-09-151-6/+20
| | | | | | libcalls, as in this testcase on ARM. llvm-svn: 56226
* Define CallSDNode, an SDNode subclass for use with ISD::CALL.Dan Gohman2008-09-135-59/+73
| | | | | | | | | | | | | Currently it just holds the calling convention and flags for isVarArgs and isTailCall. And it has several utility methods, which eliminate magic 5+2*i and similar index computations in several places. CallSDNodes are not CSE'd. Teach UpdateNodeOperands to handle nodes that are not CSE'd gracefully. llvm-svn: 56183
* Change ConstantSDNode and ConstantFPSDNode to use ConstantInt* andDan Gohman2008-09-125-14/+22
| | | | | | | | | | | | | | | | | | | | | | | | ConstantFP* instead of APInt and APFloat directly. This reduces the amount of time to create ConstantSDNode and ConstantFPSDNode nodes when ConstantInt* and ConstantFP* respectively are already available, as is the case in SelectionDAGBuild.cpp. Also, it reduces the amount of time to legalize constants into constant pools, and the amount of time to add ConstantFP operands to MachineInstrs, due to eliminating ConstantInt::get and ConstantFP::get calls. It increases the amount of work needed to create new constants in cases where the client doesn't already have a ConstantInt* or ConstantFP*, such as legalize expanding 64-bit integer constants to 32-bit constants. And it adds a layer of indirection for the accessor methods. But these appear to be outweight by the benefits in most cases. It will also make it easier to make ConstantSDNode and ConstantFPNode more consistent with ConstantInt and ConstantFP. llvm-svn: 56162
* Pass "earlyclobber" bit through to machineDale Johannesen2008-09-122-3/+14
| | | | | | | representation; coalescer and RA need to know about it. No functional change. llvm-svn: 56161
* Rename ConstantSDNode::getValue to getZExtValue, for consistencyDan Gohman2008-09-1211-128/+143
| | | | | | | with ConstantInt. This led to fixing a bug in TargetLowering.cpp using getValue instead of getAPIntValue. llvm-svn: 56159
* The sequence for ppcf128 compares was not IEEEDale Johannesen2008-09-121-4/+6
| | | | | | safe in the presence of NaNs. llvm-svn: 56136
* FastISel support for i1 PHI nodes.Dan Gohman2008-09-101-2/+7
| | | | llvm-svn: 56069
* FastISel support for i1 constants.Dan Gohman2008-09-101-2/+10
| | | | llvm-svn: 56068
* Add X86FastISel support for static allocas, and refencesDan Gohman2008-09-102-14/+23
| | | | | | | to static allocas. As part of this change, refactor the address mode code for laods and stores. llvm-svn: 56066
* Add a break statement that I accidentally deleted whenDan Gohman2008-09-101-0/+1
| | | | | | | I shuffled the fast-isel command-line options around. This fixes a bunch of fast-isel failures. llvm-svn: 56057
* Remove unnecessary bit-wise AND from the limited precision work.Bill Wendling2008-09-101-6/+4
| | | | llvm-svn: 56049
* Fix 80 col violation.Daniel Dunbar2008-09-101-1/+2
| | | | llvm-svn: 56048
* Check that both operands are f32 before attempting to lower.Bill Wendling2008-09-101-0/+1
| | | | llvm-svn: 56036
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