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* Revamp the SjLj "dispatch setup" intrinsic.Bill Wendling2011-04-051-1/+1
| | | | | | | | | | | | It needed to be moved closer to the setjmp statement, because the code directly after the setjmp needs to know about values that are on the stack. Also, the 'bitcast' of the function context was causing a dead load. This wouldn't be too horrible, except that at -O0 it wasn't optimized out, and because it wasn't using the correct base pointer (if there is a VLA), it would try to access a value from a garbage address. <rdar://problem/9130540> llvm-svn: 128873
* Revert 123704; it broke threaded LLVM.Stuart Hastings2011-04-051-9/+15
| | | | llvm-svn: 128868
* Add a RemoveFromWorklist method to DCI. This is needed to do some complicatedCameron Zwarich2011-04-021-0/+4
| | | | | | | | transformations in target-specific DAG combines without causing DAGCombiner to delete the same node twice. If you know of a better way to avoid this (see my next patch for an example), please let me know. llvm-svn: 128758
* Add comments.Evan Cheng2011-04-011-2/+4
| | | | llvm-svn: 128730
* Assign node order numbers to results of call instruction lowering. This ↵Evan Cheng2011-04-011-4/+8
| | | | | | should improve src line debug info when sdisel is used. rdar://9199118 llvm-svn: 128728
* Issue libcalls __udivmod*i4 / __divmod*i4 for div / rem pairs.Evan Cheng2011-04-012-19/+154
| | | | | | rdar://8911343 llvm-svn: 128696
* Turn SelectionDAGBuilder::GetRegistersForValue into a local function.Benjamin Kramer2011-03-262-19/+16
| | | | | | | | It couldn't be used outside of the file because SDISelAsmOperandInfo is local to SelectionDAGBuilder.cpp. Making it a static function avoids a weird linkage dance. llvm-svn: 128342
* Fix for -pre-RA-sched=source.Andrew Trick2011-03-251-0/+2
| | | | | | | Yet another case of unchecked NULL node (for physreg copy). May fix PR9509. llvm-svn: 128266
* PR9535: add support for splitting and scalarizing vector ISD::FP_ROUND.Eli Friedman2011-03-232-60/+30
| | | | | | Also cleaning up some duplicated code while I'm here. llvm-svn: 128176
* Ensure that def-side physreg copies are scheduled above any other usesAndrew Trick2011-03-231-0/+9
| | | | | | | | | so the scheduler can't create new interferences on the copies themselves. Prior to this fix the scheduler could get stuck in a loop creating copies. Fixes PR9509. llvm-svn: 128164
* whitespaceAndrew Trick2011-03-231-2/+2
| | | | llvm-svn: 128163
* Added block number and name to isel debug output.Andrew Trick2011-03-231-12/+25
| | | | | | | | I'm tired of doing this manually for each checkout. If anyone knows a better way debug isel for non-trivial tests feel free to revert and let me know how to do it. llvm-svn: 128132
* Grammar-o.Eric Christopher2011-03-211-1/+1
| | | | llvm-svn: 128004
* Add support for legalizing UINT_TO_FP of vectors on platforms which doNadav Rotem2011-03-191-1/+48
| | | | | | | | not have native support for this operation (such as X86). The legalized code uses two vector INT_TO_FP operations and is faster than scalarizing. llvm-svn: 127951
* BuildUDIV: If the divisor is even we can simplify the fixup of the ↵Benjamin Kramer2011-03-171-9/+22
| | | | | | | | | | | | | | | | | | | | | | | multiplied value by introducing an early shift. This allows us to compile "unsigned foo(unsigned x) { return x/28; }" into shrl $2, %edi imulq $613566757, %rdi, %rax shrq $32, %rax ret instead of movl %edi, %eax imulq $613566757, %rax, %rcx shrq $32, %rcx subl %ecx, %eax shrl %eax addl %ecx, %eax shrl $4, %eax on x86_64 llvm-svn: 127829
* Move more logic into getTypeForExtArgOrReturn.Cameron Zwarich2011-03-171-6/+2
| | | | llvm-svn: 127809
* Rename getTypeForExtendedInteger() to getTypeForExtArgOrReturn().Cameron Zwarich2011-03-171-1/+1
| | | | llvm-svn: 127807
* The x86-64 ABI says that a bool is only guaranteed to be sign-extended to a byteCameron Zwarich2011-03-161-5/+2
| | | | | | | | | | | rather than an int. Thankfully, this only causes LLVM to miss optimizations, not generate incorrect code. This just fixes the zext at the return. We still insert an i32 ZextAssert when reading a function's arguments, but it is followed by a truncate and another i8 ZextAssert so it is not optimized. llvm-svn: 127766
* Don't recompute something that we already have in a local variable.Cameron Zwarich2011-03-161-2/+2
| | | | llvm-svn: 127764
* sext(undef) = 0, because the top bits will all be the same.Evan Cheng2011-03-151-1/+5
| | | | | | zext(undef) = 0, because the top bits will be zero. llvm-svn: 127649
* BIT_CONVERT has been renamed to BITCAST.Evan Cheng2011-03-141-1/+1
| | | | llvm-svn: 127600
* Minor optimization. sign-ext/anyext of undef is still undef.Evan Cheng2011-03-141-0/+4
| | | | llvm-svn: 127598
* Teach FastISel to support register-immediate-immediate instructions.Owen Anderson2011-03-111-0/+23
| | | | llvm-svn: 127496
* Replace -dag-chain-limit flag with constant. It has survived a release cycle ↵Andrew Trick2011-03-111-3/+1
| | | | | | without being touched, so no longer needs to pollute the hidden-help text. llvm-svn: 127468
* Avoid replacing the value of a directly stored load with the stored value if ↵Evan Cheng2011-03-111-2/+1
| | | | | | the load is indexed. rdar://9117613. llvm-svn: 127440
* Re-commit 127368 and 127371. They are exonerated.Evan Cheng2011-03-102-10/+23
| | | | llvm-svn: 127380
* Revert 127368 and 127371 for now.Evan Cheng2011-03-092-23/+10
| | | | llvm-svn: 127376
* Change the definition of TargetRegisterInfo::getCrossCopyRegClass to be moreEvan Cheng2011-03-092-10/+23
| | | | | | | | | | | | | flexible. If it returns a register class that's different from the input, then that's the register class used for cross-register class copies. If it returns a register class that's the same as the input, then no cross- register class copies are needed (normal copies would do). If it returns null, then it's not at all possible to copy registers of the specified register class. llvm-svn: 127368
* Improve pre-RA-sched register pressure tracking for duplicate operands.Andrew Trick2011-03-091-1/+5
| | | | | | This helps cases like 2008-07-19-movups-spills.ll, but doesn't have an obvious impact on benchmarks llvm-svn: 127347
* Fix typo, make helper static.Benjamin Kramer2011-03-091-3/+3
| | | | llvm-svn: 127335
* Fix some latent bugs if the nodes are unschedulable. We'd gotten awayEric Christopher2011-03-082-1/+10
| | | | | | | | | | | | with this before since none of the register tracking or nightly tests had unschedulable nodes. This should probably be refixed with a special default Node that just returns some "don't touch me" values. Fixes PR9427 llvm-svn: 127263
* Further improvements to pre-RA-sched=list-ilp.Andrew Trick2011-03-081-17/+62
| | | | | | | This change uses the MaxReorderWindow for both height and depth, which tends to limit the negative effects of high register pressure. llvm-svn: 127203
* Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.Cameron Zwarich2011-03-071-1/+1
| | | | llvm-svn: 127175
* Use the correct LHS type when determining the legalization of a shift's RHS ↵Owen Anderson2011-03-072-5/+8
| | | | | | type. llvm-svn: 127163
* Typo.Eric Christopher2011-03-061-1/+1
| | | | llvm-svn: 127131
* Disable a couple of experimental heuristics to get the best results from the ↵Andrew Trick2011-03-061-2/+2
| | | | | | current implementation of -pre-RA-sched=list-ilp. llvm-svn: 127113
* Be explicit with abs(). Visual Studio workaround.Andrew Trick2011-03-051-4/+6
| | | | llvm-svn: 127075
* Fix for -sched-high-latency-cycles in sched=list-ilp mode.Andrew Trick2011-03-051-1/+3
| | | | llvm-svn: 127071
* Missing comment.Andrew Trick2011-03-051-0/+2
| | | | llvm-svn: 127068
* Increased the register pressure limit on x86_64 from 8 to 12Andrew Trick2011-03-052-23/+156
| | | | | | | | | | | | | | | | | | | | | | | regs. This is the only change in this checkin that may affects the default scheduler. With better register tracking and heuristics, it doesn't make sense to artificially lower the register limit so much. Added -sched-high-latency-cycles and X86InstrInfo::isHighLatencyDef to give the scheduler a way to account for div and sqrt on targets that don't have an itinerary. It is currently defaults to 10 (the actual number doesn't matter much), but only takes effect on non-default schedulers: list-hybrid and list-ilp. Added several heuristics that can be individually disabled for the non-default sched=list-ilp mode. This helps us determine how much better we can do on a given benchmark than the default scheduler. Certain compute intensive loops run much faster in this mode with the right set of heuristics, and it doesn't seem to have much negative impact elsewhere. Not all of the heuristics are needed, but we still need to experiment to decide which should be disabled by default for sched=list-ilp. llvm-svn: 127067
* Revert commit 126684 "Use the correct shift amount type". It is only the ↵Duncan Sands2011-03-041-1/+1
| | | | | | | | | | | correct type after type legalization has completed. Before then it may simply not be big enough to hold the shift amount, particularly on x86 which uses a very small type for shifts (this issue broke stuff in the past which is why LegalizeTypes carefully uses a large type for shift amounts). llvm-svn: 127000
* Minor pre-RA-sched fixes and cleanup.Andrew Trick2011-03-041-7/+15
| | | | | | | | Fix the PendingQueue, then disable it because it's not required for the current schedulers' heuristics. Fix the logic for the unused list-ilp scheduler. llvm-svn: 126981
* There are times when the landing pad won't have a call to 'eh.selector' inBill Wendling2011-03-031-9/+23
| | | | | | | | | | | | | | it. It's been assumed up til now that it would be in its immediate successor. However, this isn't necessarily the case. It could be in one of its successor's successors. Modify the code to more thoroughly check for an 'eh.selector' call in successors. It only looks at a successor if we get there as a result of an unconditional branch. Testcase ObjC/exceptions-4.m in r126968. llvm-svn: 126969
* Revert r123908; the code in question is completely untested and wrong.Eli Friedman2011-03-032-28/+0
| | | | llvm-svn: 126964
* Avoid exponential blow-up when printing DAGs.Bob Wilson2011-03-021-2/+5
| | | | | | | | | | | | | David Greene changed CannotYetSelect() to print the full DAG including multiple copies of operands reached through different paths in the DAG. Unfortunately this blows up exponentially in some cases. The depth limit of 100 is way too high to prevent this -- I'm seeing a message string of 150MB with a depth of only 40 in one particularly bad case, even though the DAG has less than 200 nodes. Part of the problem is that the printing code is following chain operands, so if you fail to select an operation with a chain, the printer will follow all the chained operations back to the entry node. llvm-svn: 126899
* Can't introduce floating-point immediate constants after legalization.Stuart Hastings2011-03-021-2/+6
| | | | | | Radar 9056407. llvm-svn: 126864
* Add a few missed unary cases when legalizing vector results. Put some casesDuncan Sands2011-03-011-31/+43
| | | | | | in alphabetical order. llvm-svn: 126745
* trailing whitespace.Jim Grosbach2011-03-011-1/+1
| | | | llvm-svn: 126733
* Generalize the register matching code in DAGISel a bit.Jim Grosbach2011-03-011-0/+12
| | | | llvm-svn: 126731
* Use the correct shift amount type.Owen Anderson2011-02-281-1/+1
| | | | llvm-svn: 126684
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